• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.29-36
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• 2009

Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.