• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.16-21
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• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.76-85
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.4
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• pp.39-46
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has l.04[pF] resolution and can be used as a touch key.

• Current Industrial and Technological Trends in Aerospace
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• v.8 no.1
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• pp.77-85
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• 2010

The current GPS constellation consists of 32 Block IIA/IIR/IIR-M satellites including 12 Block IIA satellites on service over 15 years. The satellites in poor space conditions may suffer from anomalies, especially influenced by aging atomic clocks which are of importance positioning and timing. Recently, the IGS Ultra-rapid predicted products have not shown acceptably high quality prediction performance because the Block IIA cesium clocks may be easily affected by various factors such as temperature and environment. The anomalies of aging clocks involve lower performance of positioning in the GPS applications. We, thus, describe satellite clock behaviors and anomalies induced by aging clocks and their detection technologies to avoid such anomalies.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.216-223
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• 2005

A computer clock has limits in accuracy and precision affected by its inherent instability, the environment elements, the modification of users, and errors of the system. So the computer clock needs to be synchronized with a standard clock if the computer system requires the precise time processing. The purpose of synchronizing clocks is to provide a global time base throughout a distributed system. Once this time base exists, transactions among members of distributed system can be controlled based on time. This paper discusses the integrated approach to clock synchronization. An embedded system is considered for time synchronization based on the GPS(Global Positioning System) referenced time distribution model. The system uses GPS as standard reference time source and offers UTC(Universal Time Coordinated) through NTP(Network Time Protocol). A clock model is designed and adapted to keep stable time and to provide accurate standard time with precise resolution. Private MIB(Management Information Base) is defined for network management. Implementation results and performance analysis are also presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.133-140
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• 2020

We discuss the method of a high precision range trigger and generation for a high range resolution radar. To verify the designed range resolution performance, we use test-equipments which can absolutely make a precision range shorter than the desined range resolution. The accuracy of generated range is proportional to the system reference clock. However, the system main processor is limited to input reference clocks and a higher available one is expensive in the conventional method. To solve this problem, we proposed that the range trigger and generation method using multi-phase-shiftings and integration. Through a experiment, we verified that the proposed method made problems which can be ocurred in the conventional method clear.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.203-206
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• 2002

One of the ever-increasing demands on the performances of heterodyne interferometers is to improve the measurement resolution, of which current state-of-the-art reaches the region of sub-nanometers. We propose a new scheme of phase-measuring electronics that reduces the measurement resolution without further increase in clock speed. Our scheme adopts a super-heterodyne technique that lowers the original beat frequency to a level of 1 MHz by mixing it with electrically generated reference signal. The technique enables us to measure the phase of Doppler shift with a resolution of 1.58 nanometer at a sampling rate of 1 MHz. To avoid the undesirable decrease in the maximum measurable speed caused by the lowered beat frequency, a special from of frequency up-down counting technique is combined with the super-heterodyning. This alloys performing required phase unwrapping simply by using programmable digital gates without 2$\pi$ ambiguities up to the maximum velocity of 2.35 m/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.368-373
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• 2004

Extremely fine tine resolution of ultra-wideband (UWB) signal poses a new problems to the system designer. A reasonable accuracy of the system clock is necessary to process signals with such a high space resolution. A useful way of illustrating the time resolution of a signal is to evaluate the ambiguity function. The ambiguity function for carrierless UWB defined using the time mismatch and time scaling factor as its two parameters. The UWB ambiguity function is evaluated for various signaling schemes of impulse radio.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.