• Journal of Positioning, Navigation, and Timing
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• 제11권4호
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• pp.251-261
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• 2022

The Centimeter Level Augmentation Service (CLAS) is the Precise Point Positioning (PPP) - Real Time Kinematic (RTK) correction service utilizing the Quasi-Zenith Satellite System (QZSS) L6 (1278.65 MHz) signal to broadcast the Global Navigation Satellite System (GNSS) error corrections. Compact State-Space Representation (CSSR) corrections for mitigating GNSS measurement error sources such as satellite orbit, clock, code and phase biases, tropospheric error, ionospheric error are estimated from the ground segment of QZSS CLAS using the code and carrier-phase measurements collected in the Japan's GNSS Earth Observation Network (GEONET). Since the CLAS service begun on November 1, 2018, users with dedicated receivers can perform cm-level precise positioning using CSSR corrections. In this paper, CLAS-based VRS-RTK performance evaluation was performed using Global Positioning System (GPS) observables collected from the refence station, TSK2, located in Japan. As a result of performing GPS-only RTK positioning using the open-source software CLASLIB and RTKLIB, it took about 15 minutes to resolve the carrier-phase ambiguities, and the RTK fix rate was only about 41%. Also, the Root Mean Squares (RMS) values of position errors (fixed only) are about 4cm horizontally and 7 cm vertically.

• Journal of Positioning, Navigation, and Timing
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• 제10권2호
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• pp.75-82
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• 2021

Fields of high-precision positioning applications are growing fast across the mass market worldwide. Accordingly, the industry is focusing on developing methods of applying State-Space Representation (SSR) corrections on low-cost GNSS receivers. Among SSR correction types, this paper analyzes Safe Position Augmentation for Real Time Navigation (SPARTN) messages being offered by the SAfe and Precise CORrection DAta (SAPCORDA) company and validates positioning algorithms based on them. The first part of this paper introduces the SPARTN format in detail. Then, procedures on how to apply Basic-Precision Atmosphere Correction (BPAC) and High-Precision Atmosphere Correction (HPAC) messages are described. BPAC and HPAC messages are used for correcting satellite clock errors, satellite orbit errors, satellite signal biases and also ionospheric and tropospheric delays. Accuracies of positioning algorithms utilizing SPARTN messages were validated with two types of positioning strategies: Code-PPP using GPS pseudorange measurements and PPP-RTK including carrier phase measurements. In these performance checkups, only single-frequency measurements have been used and integer ambiguities were estimated as float numbers instead of fixed integers. The result shows that, with BPAC and HPAC corrections, the horizontal accuracy is 46% and 63% higher, respectively, compared to that obtained without application of SPARTN corrections. Also, the average horizontal and vertical RMSE values with HPAC are 17 cm and 27 cm, respectively.

• 한국융합학회논문지
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• 제7권5호
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• pp.15-21
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• 2016

최근 프로세서의 집적도는 급속도로 발전하고 있으나 클락 스피드는 증가하지 않는 대신에 프로세서 내의 코어 수가 늘어나고 있는 실정으로 프로그래밍 속도 향상을 위한 방법에 대한 연구가 필수적이라 할 수 있다. 이에 본 논문에서는 현재 연산 가속화를 위해 사용되는 매니 코어 프로세서의 대표적인 인텔 제온 파이의 성능 분석을 위하여 퀀텀 에스프레소를 활용하였다. 또한 제온 파이에서 MPI 실행시 랭크의 수를 변화시키면서 성능 벤치마킹을 수행하여 하드웨어적인 성능 특성을 연구하였다. 그 결과 물리 코어가 57개인 제온파이 프로세서의 하나의 코어당 4개의 작업을 처리할 때 가장 좋은 성능을 나타내고 있으며, 물리 코어 하나에 MPI 랭크수를 4개 이상 확장하면 성능향상이 거의 일어나지 않는다. 이러한 융합 기술을 통하여 퀀텀 에스프레소의 성능 향상과 제온 파이의 하드웨어적인 특성을 확인할 수 있다.

• 한국통신학회논문지
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• 제35권12B호
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• pp.1758-1765
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• 2010

본 논문은 임베디드 코어의 설계 계층을 이용한 아키텍처 탐색 방법론을 제안한다. 제안된 방법은 다양한 설계 검증과 계층적인 설계 수준에 따른 성능 측정을 고려한 체계적인 아키텍처 탐색을 수행한다. 성능 측정 도구는 설계 모듈에 관련 있는 성능 데이터를 가진 프로파일을 생성한다. 프로파일 생성기는 설계 모듈과 성능 매개변수에 대한 연관 규칙을 얻기 위해 데이터마이닝을 수행한다. 프로파일 생성기의 추론 엔진은 다음 탐색 과정의 설계 성능을 향상시키는 새로운 연관 규칙을 얻는다. 제안된 아키텍처 탐색 방법론의 효율성을 확인하기 위해 JPEG 인코더, Chen-DCT, FFT의 어플리케이션에 대한 아키텍처 탐색을 수행하였다. 제안된 방법을 이용하여 설계된 임베디드 코어는 MIPS R3000의 초기 임베디드 코어에 비해 평균 60.8%의 수행 사이클 감소를 보인다.

• 정보보호학회논문지
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• 제15권5호
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• pp.3-11
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• 2005

본 논문은 ARS 암호프로세서의 성능분석모델을 제안하였다. 제안된 모델은 M/M/1 큐잉 모델을 기반으로 포아송 분포를 트래픽 입력으로 가정하였다. 모델을 이용한 성능분석결과 1kbyte 패킷입력에서 ARS 암호화 10라운드를 1클록에 처리하게끔 설계된 파이프라인 구조가 10클록에 처리되는 비-파이프라인 구조에 비하여 $4.0\%$ 정도의 성능향상만을 확인하였다. FPGA상에서 AES 암호프로세서를 구현한 결과 파이프라인 구조는 비-파이프라인 구조와 비교하여 게이트 수는 3.5배 크게 소요되었으나 성능은 $3.5\%$의 증가만을 나타내었다. 제안된 모델은 네트워크 컴퓨터에 사용될 AES 암호프로세서 설계 시, 최적의 가격대성능비를 갖는 구조를 제시할 수 있을 것으로 기대된다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• Journal of Positioning, Navigation, and Timing
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• 제6권3호
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• pp.125-133
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• 2017

Time comparison is necessary for the verification and synchronization of the clock. Two-way satellite time and frequency (TWSTFT) is a method for time comparison over long distances. This method includes errors such as atmospheric effects, satellite motion, and environmental conditions. Ionospheric delay is one of the significant time comparison error in case of the carrier-phase TWSTFT (TWCP). Global Ionosphere Map (GIM) from Center for Orbit Determination in Europe (CODE) is used to compare with Bernese. Thin shell model of the ionosphere is used for the calculation of the Ionosphere Pierce Point (IPP) between stations and a GEO satellite. Korea Research Institute of Standards and Science (KRISS) and Koganei (KGNI) stations are used, and the analysis is conducted at 29 January 2017. Vertical Total Electron Content (VTEC) which is generated by Bernese at the latitude and longitude of the receiver by processing a Receiver Independent Exchange (RINEX) observation file that is generated from the receiver has demonstrated adequacy by showing similar variation trends with the CODE GIM. Bernese also has showed the capability to produce high resolution IONosphere map EXchange (IONEX) data compared to the CODE GIM. At each station IPP, VTEC difference in two stations showed absolute maximum 3.3 and 2.3 Total Electron Content Unit (TECU) in Bernese and GIM, respectively. The ionospheric delay of the TWCP has showed maximum 5.69 and 2.54 ps from Bernese and CODE GIM, respectively. Bernese could correct up to 6.29 ps in ionospheric delay rather than using CODE GIM. The peak-to-peak value of the ionospheric delay for TWCP in Bernese is about 10 ps, and this has to be eliminated to get high precision TWCP results. The $10^{-16}$ level uncertainty of atomic clock corresponds to 10 ps for 1 day averaging time, so time synchronization performance needs less than 10 ps. Current time synchronization of a satellite and ground station is about 2 ns level, but the smaller required performance, like less than 1 ns, the better. In this perspective, since the ionospheric delay could exceed over 100 ps in a long baseline different from this short baseline case, the elimination of the ionospheric delay is thought to be important for more high precision time synchronization of a satellite and ground station. This paper showed detailed method how to eliminate ionospheric delay for TWCP, and a specific case is applied by using this technique. Anyone could apply this method to establish high precision TWCP capability, and it is possible to use other software such as GIPSYOASIS and GPSTk. This TWCP could be applied in the high precision atomic clocks and used in the ground stations of the future domestic satellite navigation system.

• 대한전자공학회논문지SD
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• 제47권9호
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• pp.7-13
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• 2010

본 논문은 스마트폰, 타블렛 PC와 같은 개인용 정보 단말장치 응용에 적합한 프로세서 구조를 제안한다. 고성능 내장형 프로세서 개발은 아키텍쳐의 변화가 필요하고, 오버헤드가 크기 때문에, 업계에서는 높은 동작 주파수의 고성능 내장형 프로세서의 개발에 전념하고 있다. 고성능 프로세서 구조 중 비순차 슈퍼스칼라(out-of-order superscalar)는 하드웨어 복잡도가 과도하게 증가하며, 그에 비해 성능 향상이 적으므로 내장형 응용에 적합하지 않다. 따라서 하드웨어 복잡도가 낮은 고성능 내장형 프로세서 구조의 개발이 필요하다. 본 논문에서는 스칼라, 슈퍼스칼라, 멀티프로세서 방식에 비하여 복잡도가 낮은 새로운 SMT(Simultaneous Multi-Threading) 구조를 제안한다. 최근의 개인용 정보단말기는 많은 작업을 동시에 수행하기 때문에, SMT나 CMP는 이에 적합한 구조라 할 수 있다. 또한, 시뮬레이션 결과 SMT는 여러 프로세서 구조 중 가장 효율이 높은 프로세서로 보인다.

• 대한통합의학회지
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• 제8권2호
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• pp.89-95
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• 2020

Purpose : This study aims to evaluate the correlation of cognitive function, activities of daily living (ADL), and driving performance in stroke hemiplegic patients residing in Korea. Methods : Subjects of the study were 18 stroke hemiplegic patients admitted to hospitals situated in Seoul. A clock drawing test (CDT), a modified Barthel index (MBI), and a virtual reality driving simulator (Eca faros-driving simulator) were used to examine their cognitive function, their ADL ability, and their driving skills, respectively. Results : Driving skills of stroke hemiplegic patients were shown to be associated with the CDT evaluation tool (r=-.777) (p<.001), but they were found to have any correlation with MBI (r=-.022) (p>.05). Additionally, an individual's CDT showed that the driving simulator evaluation result (pass/fail) could be discriminated with a sensitivity of 100.0 %, a specificity of 40.0 %, and an accuracy of 66.7 %. The result confirmed that the CDT is a useful evaluation tool for screening driving ability in people with stroke. But the MBI did not show any significant results (sensitivity of 62.5 %, specificity of 40.0 %, and predicted the results of the simulator with 50.0 % of accuracy) (p>.05). Conclusion : This study shows that cognitive function influences the driving performance in people with stroke. Driving skills of stroke hemiplegic patients are seen to be highly related to CDT. In the field of driving rehabilitation, these findings could be useful for evaluating driving skills relating to CDT. Furthermore, the study results will set a guideline for domestic occupational therapists to use the evaluation tool for assessing driving abilities in people with stroke.

• 대한공간정보학회지
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• 제20권3호
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• pp.49-56
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• 2012

GPS의 신뢰성 확보를 위한 무결성 모니터링기법 중 RAIM(Receiver Autonomous Integrity Monitoring) 기법에 대한 비교 실험을 수행하였다. RAIM은 사용자 단독으로 무결성을 모니터링 할 수 있는 방법으로 기존의 RAIM 기법들 중 대표 적인 방법인 거리비교방법, 최소자승잔차법, 패리티기법 그리고 가중최소자승법을 구현하고 그 성능을 평가하였다. 구현된 알고리즘의 평가를 위하여 2004년 1월 1일 PRN23번 위성시계고장에 대한 고장검출을 실시하였고 그 결과 최소자승잔차법과 가중최소자승법이 고장상태를 100% 감지하는 것을 확인하였다. 거리비교방법의 경우에도 1개 에폭에서 오경보가 발생한 오류를 제외하면 고장상태를 비교적 잘 감지하는 것으로 나타났다. 또한 위성 별로 임의의 바이어스를 입력하여, 구현된 4개의 RAIM 기법이 바이어스에 반응하는 정도를 비교하였다. 그 결과 거리비교방법과 최소자승잔차법에서 9-13m 바이어스를 입력하였을 때 모든 위성의 오작동을 감지하였고 가중최소자승법의 경우에는 15m 바이어스 크기에서 모든 위성의 오작동을 감지하였다.