• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of IKEEE
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• v.28 no.1
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• pp.53-64
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• 2024

With the advancement of NLP(Natural Language Processing) models, conversational AI such as ChatGPT is becoming increasingly popular. To enhance processing speed and reduce power consumption, it is important to implement the Transformer algorithm, which forms the basis of the latest natural language processing models, in hardware. In particular, the multi-head attention and feed-forward network, which analyze the relationships between different words in a sentence through matrix multiplication, are the most computationally intensive core algorithms in the Transformer. In this paper, we propose a new variable systolic array based on the number of input words to enhance matrix multiplication speed. Quantization maintains Transformer accuracy, boosting memory efficiency and speed. For evaluation purposes, this paper verifies the clock cycles required in multi-head attention and feed-forward network and compares the performance with other multipliers.