• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.385-390
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• 2017

Owing to the development of IT technology, a computerized system in various ways such as a variety of company's businesses, factory automation system and hospital healthcare system is introduced and operated. And it is possible to say that a computer system is more important than anything else to the extent that all businesses are suspended in case the system is down. Attention should be always paid to environmental management such as temperature, humidity and fire in server room for the normal operation of system in this situation. It is thought that there is necessity for a low-cost system which independently monitors environment round the clock in the situation where the person in charge doesn't pay attention and which informs a person in charge in real time when an event occurs for the operation of this small server room. Consequently, it is to be hoped that the suspension of service provided by computer system, which may occur due to a specific event, can be prevented.

• Dementia and Neurocognitive Disorders
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• v.22 no.4
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• pp.148-157
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• 2023

Background and Purpose: Episodic memory is a system that receives and stores information about temporally dated episodes and their interrelations. Our study aimed to investigate the relevance of episodic memory to time perception, with a specific focus on simultaneity/order judgment. Methods: Experiment 1 employed the simultaneity judgment task to discern differences in time perception between patients with mild cognitive impairment or dementia, and age-matched normals. A mathematical analysis capable of estimating subjects' time processing was utilized to identify the sensory and decisional components of temporal order and simultaneity judgment. Experiment 2 examined how differences in temporal perception relate to performance in temporal order memory, in which time delays play a critical role. Results: The temporal decision windows for both temporal order and simultaneity judgments exhibited marginal differences between patients with episodic memory impairment, and their healthy counterparts (p = 0.15, t(22) = 1.34). These temporal decision windows may be linked to the temporal separation of events in episodic memory (Pearson's ρ = -0.53, p = 0.05). Conclusions: Based on our findings, the frequency of visual events accumulated and encoded in the working memory system in the patients' and normal group appears to be approximately (5.7 and 11.2) Hz, respectively. According to the internal clock model, a lower frequency of event pulses tends to result in underestimation of event duration, which phenomenon might be linked to the observed time distortions in patients with dementia.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Korean Journal of Agricultural and Forest Meteorology
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• v.19 no.3
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• pp.164-173
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• 2017

Alternative cropping systems would be one of climate change adaptation options. Suitable areas for a crop could be identified using a climate suitability model. The EcoCrop model has been used to assess climate suitability of crops using monthly climate surfaces, e.g., the digital climate map at high spatial resolution. Still, a high-performance computing approach would be needed for assessment of climate suitability to take into account a complex terrain in Korea, which requires considerably large climate data sets. The objectives of this study were to implement a script for R, which is an open source statistics analysis platform, in order to use the EcoCrop model under a parallel computing environment and to assess climate suitability of maize using digital climate maps at high spatial resolution, e.g., 1 km. The total running time reduced as the number of CPU (Central Processing Unit) core increased although the speedup with increasing number of CPU cores was not linear. For example, the wall clock time for assessing climate suitability index at 1 km spatial resolution reduced by 90% with 16 CPU cores. However, it took about 1.5 time to compute climate suitability index compared with a theoretical time for the given number of CPU. Implementation of climate suitability assessment system based on the MPI (Message Passing Interface) would allow support for the digital climate map at ultra-high spatial resolution, e.g., 30m, which would help site-specific design of cropping system for climate change adaptation.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.99-108
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• 2011

Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of $2.3{\times}$ over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only $1.4{\times}$ over the same baseline SIMD array performance. In addition, the proposed instructions achieve $2.5{\times}$ better energy efficiency than the baseline program, while MMX-type instructions achieve only $1.8{\times}$ better energy efficiency than the baseline program.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of Korea Water Resources Association
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• v.44 no.12
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• pp.991-1000
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• 2011

The relationship between discharge (Q) and suspended sediment (SS) concentration often is used for the estimation of inflow SS concentration in reservoir turbidity modeling in the absence of actual measurements. The power function, SS=aQb, is the most commonly used empirical relation to determine the SS load assuming the SS flux is controlled by variations of discharge. However, Q-SS relation typically is site specific and can vary depending on the season of the year. In addition, the relation sometimes shows hysteresis during rising limb and falling limb for an event hydrograph. The objective of this study was to examine the hysteresis of Q-SS relationships through continuous field measurements during flood events at inflow rivers of Yongdam Reservoir and Soyang Reservoir, and to analyze its effect on the bias of SS load estimation. The results confirmed that Q-SS relations display a high degree of scatter and clock-wise hysteresis during flood events, and higher SS concentrations were observed during rising limb than falling limb at the same discharge. The hysteresis caused significant bias and underestimation of SS loading to the reservoirs when the power function is used, which is important consideration in turbidity modeling for the reservoirs. As an alternative of Q-SS relation, turbidity-SS relation is suggested. The turbidity-SS relations showed less variations and dramatically reduced the bias with observed SS loading. Therefore, a real-time monitoring of inflow turbidity is necessary to better estimate of SS influx to the reservoirs and enhance the reliability of reservoir turbidity modeling.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.176-182
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• 2014

This paper introduces the development of global fringe search (GFS) software for preprocessing of Daejeon Correlator. In case of the VLBI observation, a observer conducts the observation for the reference sources with strong and point-like radio stars on schedule in order to confirm the well-observedness of the radio source by the radio telescope. The correlator performs the correlation for the reference sources to detect the fringe completely. We developed the GFS software by calculating the precise delay time between each observatory based on specific observatory. Then, this software calculates the precise delay time by using the delay model (correlator model) of reference source and information of time offset between the Hydrogen Maser frequency standard and GPS (Global Positioning System) clock located in each observatory through the correlation preprocessing. In order to confirm the performance of the developed software, experiments were carried out for the reference sources and target sources observed by the KaVA (KVN and VERA Array). Experimental results show that the GFS software has effectively good performance by finding the precise delay time offset according to the comparison between the compensated delay time offset and one without compensation.