• Publications of The Korean Astronomical Society
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• v.35 no.3
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• pp.43-57
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• 2020

Hong, Dae-Yong manufactured the Tongcheon-ui (Pan-celestial Armillary Sphere) with cooperating clock researcher Na, Kyeong-Jeok, and its craftsman An, Cheo-In, in Naju of Jeolla Province in 1760 ~ 1762. Tongcheon-ui is a kind of astronomical clock with an armillary sphere which is rotated by the force generated by a lantern clock's weight. In our study, we examine the lantern clock model of Tongcheon-ui through its description of the articles written by Hong himself. As his description, however, did not explain the detail of the mechanical process of the lantern clock, we investigate the remains of lantern clocks in the possession of Korea University Museum and Seoul National University Museum. Comparing with the clocks of these museums, we designed the lantern clock model of Tongcheon-ui which measures 115 mm (L) × 115 mm (W) × 307 mm (H). This model has used the structure of the striking train imitated from the Korea University Museum artifact and is also regulated by a foliot escapement which is connected to a going train for timekeeping. The orientation of the rotation of the going train and the striking train of our model makes a difference with the remains of both university museums. That is, on the rotation axis of the first gear set of Tongcheon-ui's lantern clock, the going and the striking trains take on a counterclockwise and clockwise direction, respectively. The weight of 6.4 kg makes a force driving these two trains to stick to the pulley on the twine pulling across two spike gears corresponding to the going train and the striking train. This weight below the pulley may travel down about 560 mm per day. We conclude that the mechanical system of Tongcheon-ui's lantern clock is slightly different from the Japanese style.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.220-227
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• 2017

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• BMB Reports
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• v.49 no.11
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• pp.587-589
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• 2016

The circadian clock system enables organisms to anticipate the rhythmic environmental changes and to manifest behavior and physiology at advantageous times of the day. Transcriptional/translational feedback loop (TTFL) is the basic feature of the eukaryotic circadian clock and is based on the rhythmic association of circadian transcriptional activator and repressor. In Drosophila, repression of dCLOCK/CYCLE (dCLK/CYC) mediated transcription by PERIOD (PER) is critical for inducing circadian rhythms of gene expression. Pacemaker neurons in the brain control specific circadian behaviors upon environmental timing cues such as light and temperature cycle. We show that amino acids 657-707 of dCLK are important for the transcriptional activation and the association with PER both in vitro and in vivo. Flies expressing dCLK lacking AA657-707 in $Clk^{out}$ genetic background, homologous to the mouse Clock allele where exon 19 region is deleted, display pacemaker-neuron-dependent perturbation of the molecular clockwork. The molecular rhythms in light-cycle-sensitive pacemaker neurons such as ventral lateral neurons ($LN_vs$) were significantly disrupted, but those in temperature-cycle-sensitive pacemaker neurons such as dorsal neurons (DNs) were robust. Our results suggest that the dCLK-controlled TTFL diversify in a pacemaker-neuron-dependent manner which may contribute to specific functions such as different sensitivities to entraining cues.

• ETRI Journal
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• v.34 no.1
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• pp.35-43
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• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• Journal of Positioning, Navigation, and Timing
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• v.8 no.4
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• pp.209-214
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• 2019

Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.487-491
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• 2008

This paper proposes the Byzantine fault tolerant clock synchronization scheme for wireless sensor networks to cope with the clock synchronization disturbance attack of malicious nodes. In the proposed scheme, a node which is requiring clock synchronization receives 3m+1 clock synchronization messages not only from its parent nodes but also from its sibling nodes in order to tolerate malicious attacks even if up to m malicious nodes exist among them. The results show that the proposed scheme is 7 times more resilient to the clock synchronization disturbance attack of malicious nodes than existing schemes in terms of synchronization accuracy.

• Journal of the Korea Society of Computer and Information
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• v.13 no.1
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• pp.175-183
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• 2008

QoS-support technology in networks is based on measuring QoS metrics which reflect a magnitude of stability and performance. The one-way delay measurement of the QoS metrics especially requires a guarantee of clock synchronization between end-to-end hosts. However, the hosts in networks have a relative or absolute difference in clock time by reason of clock offsets. flock skews and clock adjustments. In this paper, we present a theorem, methods and simulation results of one-way delay and clock offset estimations between end-to-end hosts. The proposed theorem is a relationship between one-way delay, one-way delay variation and round-trip time And we show that the estimation error is mathematically smaller than a quarter of round-trip time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.63-68
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• 2004

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.