• 한국정밀공학회지
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• 제7권3호
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• pp.94-102
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• 1990

A computer software which can draw and analyze pneumatic circuits was developed for the purpose of introducing and educating pneumatic circuits to beginners in this field. The program was developed using Turbo Pascal and Turbo Pascal Graphix Toolbox and could be run on IBM PC, XT, AT and other IBM compatible computers with a Hercules Graphics Board. The program was defeloped to show sequential control characteristics and to show two stages(on and off) of the pneumatic actuators. Users may save much time in drawing complex pneumatic circuits and can also use this software to check whether circuits are property designed before constucting real pneumatic circuits.

• 전기학회논문지P
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• 제62권2호
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• 전자공학회논문지A
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• 제31A권4호
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• pp.99-105
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• 1994

k-bounded circuits are combinational circuits proposed by Fujiwara whose subcircuits are partitioned in a way that they form a tree and have some restricted k inputs respectively. Fujiwara proposed a O($16^{k}m$) fault detection algorithm for k-bounded circuits where m is the number of signal lines in the circuit. This algorithm is very ineffective to be applied to real circuits, even for small values of k. In this paper, it is shown that a single stuck-at fault in k-bounded circuits can be detected in O($2^{k}m$)time, and multiple stuck-at faults are detected in O($4^{k}m$) time by using thable lookup and imput partitionsing.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 정기총회 및 창립40주년기념 학술대회 학회본부
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• pp.547-551
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• 1987

New chopper circuits for decoupled operation of the dc series motor are presented. These new choppers are capable of controlling field current completely separately, while offering capability of bidirectional armature energy flow. To develop the chopper circuit, with minimum number of switching elements, the complete family of possible conduction circuits are systematically investigated. Then one or two quadrant chopper circuits which offer the desired operations are synthesized from the resulting conduction circuits. Finally, the developed chopper circuits are completely analyzed. The details of operation of the chopper circuits are also fully described.

• 대한전기학회논문지
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• 제38권10호
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• pp.832-839
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• 1989

New chopper circuits for decoupled operation of the dc series motor are presented. These new choppers are capable of controlling field current completely separately, while offering capability of bidirectional armature energy flow. To develop the chopper circuit with minimum number of swithcing elements, the complete family of possible conduction circuits are systematically investigated. Then one or two quadrant chopper circuits which offer the desired operations are synthesized from the resulting conduction circuits. Finally, the developed chopper circuits are analyzed in the steady state. The details of operation of the chopper circuits are also fully described and experimented.

• 대한전기학회논문지
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• 제43권3호
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• pp.504-514
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• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• ETRI Journal
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• 제41권3호
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• ETRI Journal
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• 제27권5호
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• pp.569-578
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• 2005

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

• 전기학회논문지
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• 제58권11호
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• pp.2168-2174
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• 2009

Electrical railway system consists of rolling stock, track, signal and streetcar line system. Track circuit system is a vital system due to checking the location of trains. Track circuits are divided by using frequency and isolated electrically. Currently, there is not a regulation for the distance between track circuits using identical frequency. In case of installing additional track circuits in large stations or marshalling yard, the problem which is that the signal is not exactly transmitted to the track circuit occurs due to the mutual interference. In other words, the track circuit properly is not operated on account of wrong induction current by the mutual inductance between track circuits. In this paper, we suggest the electrical model between track circuits and numerically calculate demanded parameters in electrical model. The distance between track circuits satisfying the mutual inductance which does not happen to the mutual interference phenomenon is presented about the distance of track circuit. It is proved by using Matlab and PSpice program as the amplitude of mutual induced current.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.674-677
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• 2000

Operational principles and driving characteristics of two well-known energy recovery circuits for ac plasma display panels Weber and Sakai circuits are investigated Efficiency of two circuits is analyzed by comparing the in put current of the circuits with different operating conditions. Driving characteristics of the Weber circuit are studied when the magnitude and pulse width of the driving boltage very.