• Journal of the Korean Society for Precision Engineering
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• v.27 no.10
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• pp.14-22
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• 2010

The most costly and time-consuming process in the fabrication of today's multi-layer circuit board is drilling interconnection holes between adjacent layers and via holes within a layer. Decreasing size of via holes being demanded and growing number of via holes per panel increase drilling costs. Component density and electronic functionality of today's multi-layer circuit boards can be improved with the introduction of cost-effective, variable depth laser drilled blind micro via holes, and interconnection holes. Laser technology is being quickly adopted into the circuit board industry but can be accelerated with the introduction of a true production laser drilling system. In order to get optimized condition for drilling to FPCB (Flexible Printed Circuit Board), we use various drill pattern as drill step. For productivity, we investigate drill path optimization method. And for the precise drilling the thermal drift of scanner and temperature change of scan system are tested.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.82-89
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• 2001

This paper proposes several methods to analyze dynamic and static characteristics of HVDC inverter system. The characteristic analysis is essential of the controller and filter design of the HVDC inverter system. Dynamic characteristic can be analyzed with EMTP simulation and static characteristic can be obtained by solving newly proposed load flow equation which includes the filter and load characteristic. New simple per-phase-equivalent circuit is also proposed. In this circuit, HVDC inverter is considered as a current source depending on the on-off status of switch. Dynamic and static characteristic can be analyzed by the proposed per-phase-equivalent circuit. For the optimal filter design, various performance criteria are proposed. The performance index, based on the per-phase-equivalent circuit, is calculated. Voltage harmonics and filter power loss are selected as criteria. Optimization procedure is explained to find optimal passive filter parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.474-480
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• 2003

We designed and tested a new scan driver output stage. Compared to conventional CMOS structured scan driver IC′s, the new NMOSFET-only scan driver circuit can reduce the chip area and therefore, the chip cost considerably. We confirmed the circuit operation with open drain power NMOSFET IC′s by driving 2"PDP test panel. We defined critical device parameters and their optimization methods lot the best circuit performance.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.88-93
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• 2008

The electromagnetic parameters of a permanent magnet synchronous motor (PMSM) such as the open load permanent magnet flux, d axis reactance $X_d$, and q axis reactance $X_q$, are most essential to the performance analysis and optimization design of the motor. Based on the numerical analysis of the 3D electromagnetic field, the three electromagnetic parameters of permanent magnet synchronous motors with U form interior rotor structures are calculated by FEA. The rules of the leakage coefficient and reactance parameters changing with the air gap length, permanent magnet magnetism length, and isolation magnetic bridge dimensions in the rotor are given. The calculated values agree well with the measured values. The FEA results are integrated with the self compiled electromagnetic design program to optimize the prototype motor. The tested performances of the prototype motor prove that the method is suitable for the optimization of motor structure.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.107.6-107
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• 2001

Genetic alogorithm(GA) is a well-known global optimization algorithm. However, as the searching bounds grow wider., performance of local optimization deteriorates. In this paper, we propose a hybrid algorithm which integrates the gradient algorithm and GA so as to reinforce the performance of local optimization. We apply this algorithm to the system identification of second order RLC circuit. Identification results show that the proposed algorithm gets the better and robust performance to find the exact values of RLC elements.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.4
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• pp.43-49
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• 2004

A spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of the electric contacts of a vacuum circuit breaker. If the type of a circuit breaker and the structure of the linkage system are predetermined, then design parameters such as stiffness, free length and attachment points of the spring become the important issues. In this paper, based on the energy conservation, the total system energy is constant throughout the operating range of the mechanism; a systematic procedure to optimize the spring design parameters is developed and applied to a simplified mechanism of a circuit breaker. The developed procedure is converted to the environment of the multi-body dynamics program, ADAMS for an in-depth consideration of the complex dynamics of a circuit breaker mechanism.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.3
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• pp.132-138
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• 2004

In a vacuum circuit breaker mechanism, a spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of electric contacts. If the type and structure of the linkage system required to the circuit breaker is predetermined, the stiffness, free length and attachment points of a spring become the important design parameters. In this paper, based on the energy conservation that the total system energy is constant throughout the operating range of the mechanism, a systematic procedure for optimizing the spring design parameters is developed and applied to the simplified mechanism of a circuit breaker. Then, in order to consider the complex dynamics of the circuit breaker mechanism rather well, the developed procedure is converted to the environment of a multi-body dynamics program ADAMS.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.1
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• pp.73-79
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• 2016

Higher circuit breaker safety standards can be obtained by increasing the sustaining time of the latching section. This time increase is achieved through velocity reduction after contacting when the closing mechanism operates. The potential for the re-closing phenomenon to occur is also reduced by obtaining time to return open latch. In this study, the sustaining time for the latching section was increased through cam profile optimization based on the displacement response of the moving parts. In addition, the existing performance velocity was also satisfied. A multibody dynamics model of the circuit breaker was developed using ADAMS. To validate the model, simulation results were compared to experiment results. Then, cam profile optimization was carried out using an optimal design program PIAnO. Design variables selected included the radial direction of the cam. Design sensitivity analysis was carried out by design section as well. As a result of optimization, the sustaining time for the latching section was increased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11b
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• pp.204-209
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• 2002

A PDP(Plasma Display Panel) module consists of a discharge panel, a SMPS(Switched Mode Power Supply) for power supply, driving boards for panel control, and a logic board. Driving boards supply high voltage pulses to induce glow discharge in the PDP panel. The electrical pulses excite the circuit elements and subsequently generate acoustic noises. The main sources of the noise in the circuit are the transformer of SMPS and the power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) of driving boards, and the heat sinks often amplify the noise level. The reduction of the acoustic noises was achieved by modifying both the structural and circuit elements. The structural method was executed by the improvement of heat sinks. The optimization of SMPS and condensers was carried out for the circuit elements.