• 한국정밀공학회지
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• 제27권10호
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• pp.14-22
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• 2010

The most costly and time-consuming process in the fabrication of today's multi-layer circuit board is drilling interconnection holes between adjacent layers and via holes within a layer. Decreasing size of via holes being demanded and growing number of via holes per panel increase drilling costs. Component density and electronic functionality of today's multi-layer circuit boards can be improved with the introduction of cost-effective, variable depth laser drilled blind micro via holes, and interconnection holes. Laser technology is being quickly adopted into the circuit board industry but can be accelerated with the introduction of a true production laser drilling system. In order to get optimized condition for drilling to FPCB (Flexible Printed Circuit Board), we use various drill pattern as drill step. For productivity, we investigate drill path optimization method. And for the precise drilling the thermal drift of scanner and temperature change of scan system are tested.

• 전력전자학회논문지
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• 제6권1호
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• pp.82-89
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• 2001

본 논문은, HVDC 시스템의 인버터 제어기 및 고조파 필터의 설계를 위하여 동특성 및 정상상태 특성을 해석하는 방법을 제시한다. EMTP 시뮬레이션을 이용하면, 동특성 분석이 가능하며, 정상상태 특성의 분석은필터와 부하를 고려한 조류해석을 수행함으로써 가능하다. 또한 본 논문은 HVOC 시스템의 정적 및 동적 특성 분석이 가능한 단상 등가회로를 제안한다. 이 단상 등가회로에서 인버터는 스위치의 소호에 따른 전류원으로 취급된다. 또한 필터설계에 사용되고 있는 각종 목적함수를 단상 등가회로룹 이용하여 구할 수 있다, 본 논문은 전압의 고조파 성분 및 필터의 전력손실을 고려한 목적함수를 이용하여 펄터를 최적화하는 과정이 제시되어 있다.

• 대한전자공학회논문지SD
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• 제40권7호
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• pp.474-480
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• 2003

We designed and tested a new scan driver output stage. Compared to conventional CMOS structured scan driver IC′s, the new NMOSFET-only scan driver circuit can reduce the chip area and therefore, the chip cost considerably. We confirmed the circuit operation with open drain power NMOSFET IC′s by driving 2"PDP test panel. We defined critical device parameters and their optimization methods lot the best circuit performance.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.88-93
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• 2008

The electromagnetic parameters of a permanent magnet synchronous motor (PMSM) such as the open load permanent magnet flux, d axis reactance $X_d$, and q axis reactance $X_q$, are most essential to the performance analysis and optimization design of the motor. Based on the numerical analysis of the 3D electromagnetic field, the three electromagnetic parameters of permanent magnet synchronous motors with U form interior rotor structures are calculated by FEA. The rules of the leakage coefficient and reactance parameters changing with the air gap length, permanent magnet magnetism length, and isolation magnetic bridge dimensions in the rotor are given. The calculated values agree well with the measured values. The FEA results are integrated with the self compiled electromagnetic design program to optimize the prototype motor. The tested performances of the prototype motor prove that the method is suitable for the optimization of motor structure.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.107.6-107
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• 2001

Genetic alogorithm(GA) is a well-known global optimization algorithm. However, as the searching bounds grow wider., performance of local optimization deteriorates. In this paper, we propose a hybrid algorithm which integrates the gradient algorithm and GA so as to reinforce the performance of local optimization. We apply this algorithm to the system identification of second order RLC circuit. Identification results show that the proposed algorithm gets the better and robust performance to find the exact values of RLC elements.

• International Journal of Precision Engineering and Manufacturing
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• 제5권4호
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• pp.43-49
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• 2004

A spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of the electric contacts of a vacuum circuit breaker. If the type of a circuit breaker and the structure of the linkage system are predetermined, then design parameters such as stiffness, free length and attachment points of the spring become the important issues. In this paper, based on the energy conservation, the total system energy is constant throughout the operating range of the mechanism; a systematic procedure to optimize the spring design parameters is developed and applied to a simplified mechanism of a circuit breaker. The developed procedure is converted to the environment of the multi-body dynamics program, ADAMS for an in-depth consideration of the complex dynamics of a circuit breaker mechanism.

• 한국정밀공학회지
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• 제21권3호
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• pp.132-138
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• 2004

In a vacuum circuit breaker mechanism, a spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of electric contacts. If the type and structure of the linkage system required to the circuit breaker is predetermined, the stiffness, free length and attachment points of a spring become the important design parameters. In this paper, based on the energy conservation that the total system energy is constant throughout the operating range of the mechanism, a systematic procedure for optimizing the spring design parameters is developed and applied to the simplified mechanism of a circuit breaker. Then, in order to consider the complex dynamics of the circuit breaker mechanism rather well, the developed procedure is converted to the environment of a multi-body dynamics program ADAMS.

• 대한기계학회논문집A
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• 제40권1호
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• pp.73-79
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• 2016

차단기 메커니즘의 안전성은 클로징 메커니즘 작동 시 접점 이후의 속도 감소를 통한 오픈 샤프트가 래치에 걸리는 래칭(latching) 구간에서의 유지 시간 개선을 통해 확보된다. 이는 오픈 래치가 복귀할 시간을 확보하여 재 차단되는 현상을 줄이기 때문이다. 본 연구에서는 캠 윤곽 최적화를 통해 기존의 구동 성능을 만족하고 래칭 구간에 대한 메커니즘의 안전성을 확보하고자 가동부의 변위 응답 중 래칭이 발생하는 구간에서의 유지 시간을 개선하였다. ADAMS 를 이용한 차단기 다물체동역학 모델을 개발하였으며 시험 결과와 비교하여 검증하고 최적설계 프로그램인 PIAnO 를 사용하여 캠 윤곽의 최적설계를 수행하였다. 캠 윤곽의 최적설계는 캠의 반경 방향으로 설계점을 선정하였으며 설계구간별 민감도 분석을 수행하였다. 최적화 결과 래칭 구간에서의 유지 시간을 개선하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2002년도 추계학술대회논문집
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• pp.204-209
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• 2002

A PDP(Plasma Display Panel) module consists of a discharge panel, a SMPS(Switched Mode Power Supply) for power supply, driving boards for panel control, and a logic board. Driving boards supply high voltage pulses to induce glow discharge in the PDP panel. The electrical pulses excite the circuit elements and subsequently generate acoustic noises. The main sources of the noise in the circuit are the transformer of SMPS and the power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) of driving boards, and the heat sinks often amplify the noise level. The reduction of the acoustic noises was achieved by modifying both the structural and circuit elements. The structural method was executed by the improvement of heat sinks. The optimization of SMPS and condensers was carried out for the circuit elements.