• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of IKEEE
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• v.19 no.4
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• pp.541-547
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• 2015

In current semiconductor manufacturing, as the feature size of integrated circuit (IC) devices continuously shrinks, detecting endpoint in plasma etching process is more difficult than before. For endpoint detection, various kinds of sensors are installed in semiconductor manufacturing equipments, and sensor data are gathered with predefined sampling rate. Generally, detecting endpoint is performed using OES data of by-product. In this study, OES data of both by-product and etchant gas are used to improve reliability of endpoint detection. For the OES data pre-processing, a combination of Signal to Noise Ratio (SNR) and Principal Component Analysis (PCA),are used. Polynomial Regression and Expanded Hidden Markov model (eHMM) technique are applied to pre-processed OES data to detect endpoint.

• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.79-88
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• 2015

This paper introduces surveillance equipment "ADS-B", the core subject of traffic control system and study of ADS-B 1090ES ground receiver. The standard is set not only for functional but also its reliability by analyzing international standard documents and existing products. The Bias circuit is designed for less power consumption, low noise and high gain for RF module. The signal processing is capable of overcoming its bad conditions. MCU part is configured with the latest CPU for high speed communication with external parts and SNMP is selected for remote control communication. The performance of developed receiver satisfies national and international standards and its functions are more advanced compared to foreign receivers.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.161-166
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• 1999

The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.31 no.2
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• pp.190-198
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• 1995

Many industrial servo amplifiers employ power transister as output device. Thyristor converters are not adopted to drive servo motor, although thyristor is superior to power TR in power rating, noise immunity, price, and size. The reason is, thyristor has no ability of self turn - off. Here in this paper line commutation, in which thyristor is turned off naturally since cathode voltage is higher than anode as time goes by, is employed to turn on thyristor with a delicate sequence. We developed thyristor servo amplifier which does not cause any damage on thyristor because it is designed to prevent triggering the two SCRs in the same arm simultaneously. And it was made clearly how to trigger SCR without any power line shorting and also harmonic analysis is carried out with the aid of FFT analyzer and proved that it can be used even severe reactive load. The designed circuit operated as a good DC amplifier in conventinal servomotor and the results can be use as a position control system application.

• Journal of Power Electronics
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• v.17 no.4
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• pp.892-904
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• 2017

A design of a Class-E inverter with only one inductor and one capacitor is presented. It is operated at the optimal operation mode for domestic cooker. The design principle is based on the zero-voltage derivative switching (ZVDS) of the Class-E inverter with a parallel load network, which is a parallel resonant equivalent circuit. An induction load characterization is obtained from a large-signal excitation test bench, which is the key to an accurate design of the induction cooker system. Consequently, the proposed scheme provides a more systematic, simple, accurate, and feasible solution than the conventional quasi-resonant inverter analysis based on series load network methodology. The derivative of the switch voltage is zero at the turn-on transition, and its absolute value is relatively small at the turn-off transition. Switching losses and noise are reduced. The parameters of the ZVDS Class-E inverter for the domestic induction cooker must be selected properly, and details of the design of the components of this Class-E inverter need to be addressed. A 1,200 W prototype is designed and evaluated to verify the validation of the proposed topology.