• ETRI Journal
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• v.38 no.5
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• pp.903-910
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• 2016

We propose a novel multi-stack (MS) technique for a compact and wideband electromagnetic bandgap (EBG) structure in high-speed multilayer printed circuit boards. The proposed MS technique efficiently converts planar EBG arrays into a vertical structure, thus substantially miniaturizing the EBG area and reducing the distance between the noise source and the victim. A dispersion method is presented to examine the effects of the MS technique on the stopband characteristics. Enhanced features of the proposed MS-EBG structure were experimentally verified using test vehicles. It was experimentally demonstrated that the proposed MS-EBG structure efficiently suppresses the power/ground noise over a wideband frequency range with a shorter port-to-port spacing than the unit-cell length, thus overcoming a limitation of previous EBG structures.

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.13-17
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• 2016

The ampere-hour integral method and the open circuit voltage method are integrated via the extended Kalman filter method so as to overcome insufficiencies of the ampere-hour integral method and the open circuit voltage method for estimating battery SOC. The process noise covariance and the measurement noise covariance of the extended Kalman filter method are simplified based on the Thevenin equivalent circuit model, with a proposed simplified SOC estimating method. Verification of DST experiments indicated that the battery SOC estimating method is simple and feasible, and the estimated SOC error is no larger than 2%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.2
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• pp.329-334
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• 2016

In this paper, we demonstrate a Non-Foster matching method for an electrically small antenna to improve the signal-to-noise ratio (SNR) of communication link. For the experiment, we used a general FM antenna whose resonance frequency is about 52-57 MHz and a floating type Linvill negative impedance converter(NIC)-based circuit as a Non-Foster matching element. By implementing the Non-Foster circuit to cover FM band, we can achieve a wide bandwidth matching covers 40-200 MHz. Our measurement shows 3-7 dB improvement of SNR for the same bandwidth though there are several spikes which means no improvement of SNR in the band.

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2000.06a
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• pp.1273-1279
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• 2000

A new concept of piezoelectric smart panels for noise reduction in wide band frequencies is proposed and their possibility is experimentally investigated. The proposed panels are based on active and passive methods. They use piezoelectric smart structure technology for active noise reduction at low band frequencies and passive sound absorbing materials for mid-range of noise frequencies. To prove the concept of piezoelectric smart panels, an acoustic measurement experiment was performed. The smart panels exhibit a good noise reduction in middle and high frequency ranges due to the mass effects of absorbing materials or/and the air gap. The use of piezoelectric smart panel renders noise reduction large at resonance frequency. Another concept of smart panel that uses piezoelectric damping is experimentally investigated. Since piezoelectric dampings can reduce vibration and noise at resonance frequencies with simple shunt circuit, they have merits in terms of economy and simplicity. Dissipated energy method(DEM) is adopted to tune the shunt circuit precisely in piezoelectric dampings. Noise reduction at multiple resonance frequencies is demonstrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.29-36
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• 2009

Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.

• ETRI Journal
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• v.38 no.2
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• pp.235-243
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• 2016

A low-noise readout integrated circuit (ROIC) for a microelectromechanical systems (MEMS) microphone is presented in this paper. A positive feedback signal amplification technique is applied at the front-end of the ROIC to minimize the effect of the output buffer noise. A feedback scheme in the source follower prevents degradation of the noise performance caused by both the noise of the input reference current and the noise of the power supply. A voltage booster adopts noise filters to cut out the noise of the sensor bias voltage. The prototype ROIC achieves an input referred noise (A-weighted) of -114.2 dBV over an audio bandwidth of 20 Hz to 20 kHz with a $136{\mu}A$ current consumption. The chip is occupied with an active area of $0.35mm^2$ and a chip area of $0.54mm^2$.

• Journal of electromagnetic engineering and science
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• v.15 no.2
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• pp.89-96
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• 2015

This paper describes the application of a passive noise cancellation method to a prototype inductor-inductor-capacitor (LLC) resonant converter by placing a compensation winding in a transformer to reduce common mode noise. The connection method for the compensation winding is investigated. A circuit analysis is implemented for the displacement currents between the primary and secondary windings in the transformer. The analyzed displacement currents are verified by performing a circuit simulation and a proper compensation winding connection that reduces common mode noise is found. The measurement results show that common mode noise is reduced effectively up to 20 dB in the 1 to 7 MHz frequency region for the prototype LLC resonant converter by using the proposed passive noise cancellation method.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.100-105
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• 2022

This paper applies the arc detection algorithm to prevent the false detection in photo voltaic series arc detection circuit, which is required not only to detect the series arc quickly, but also not falsely detect the arc for the non-arc noise. For this purpose, this study proposes a rapid and preventive false detection method of single peak noise and short noise signals. First, to prevent false detection by single peak noise, Discrete wavelet transform (DWT)-based characteristic parameters are applied to determine the shape and the amplitude of the noise. In addition, arc fault detection within a few milliseconds is performed with the DWT iterative algorithm to quickly prevent false detection for short noise signals, considering the continuity of serial arc noise. Thus, the method operates not only to detect series arc, but also to avoid false arc detection for peak and short noises. The proposed algorithm is applied to real-time serial arc detection circuit based on the TMS320F28335 DSP. The serial arc detection and peak noise filtering performances are verified in the built simulated arc test facility. Furthermore, the filtering performance of short noise generated through DC switch operation is confirmed.

• ETRI Journal
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• v.27 no.1
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• pp.75-80
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• 2005

This paper addresses a fully-integrated low phase noise X-band oscillator fabricated using a carbon-doped InGaP heterojunction bipolar transistor (HBT) GaAs process with a cutoff frequency of 53.2 GHz and maximum oscillation frequency of 70 GHz. The oscillator circuit consists of a negative resistance generating circuit with a base inductor, a resonating emitter circuit with a microstrip line, and a buffering resistive collector circuit with a tuning diode. The oscillator exhibits 4.33 dBm output power and achieves -127.8 dBc/Hz phase noise at 100 kHz away from a 10.39 GHz oscillating frequency, which benchmarks the lowest reported phase noise achieved for a monolithic X-band oscillator. The oscillator draws a 36 mA current from a 6.19 V supply with 47.1 MHz of frequency tuning range using a 4 V change. It occupies a $0.8mm{\times}0.8mm$ die area.