• The Journal of Korean Institute of Communications and Information Sciences
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• v.6 no.1
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• pp.32-37
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• 1981

The novel design method of ternary rate multiplier is proposed. This paper sugests the new implementation technique of multiplier implemented by the technique is capable of working at higher spced than that of the ternary counter type. This technique is intended to use the binary elements except the ternary inverter. And also, the mordetn COS/MOS integration process can easily implement the circuit designed by this method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• ETRI Journal
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• v.27 no.3
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• pp.337-340
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• 2005

A spot-size converted Fabry-Perot laser diode (LD) was flip-chip bonded to a silica-terraced planar lightwave circuit(PLC) platform to examine the effect of the silica terrace on the heat dissipation of the LD module. From the measurement of the light-current characteristics, it was discovered that the silica terrace itself is not a strong thermal barrier, but the encapsulation of the integrated LD with an index-matching polymer resin more or less deteriorates the heat dissipation.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.921-926
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• 2003

This paper describes a new type of the spatial filter detector (SFD) with variable and multi-valued weighting function. This SFD called variable spatial filter detector with multi-valued weighting function (VSFDwMWF) uses current-mode circuits for noise resistance and high-resolution weighting values. Total weighting values consist of 7bit, 6-signal bit and 1-sign bit. We fabricate VSFDwMWF chip using Rohm 0.35${\mu}$m CMOS process. VSFDwMWF chip includes two-dimensional 10${\times}$13 photodiode array and current-mode weighting control circuit. Simulation shows the weighting values are varied and multi-valued by external switching operation. The layout of VSFDwMWF chip is shown.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.236-250
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• 2016

Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

• ETRI Journal
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• v.37 no.1
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• pp.61-65
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• 2015

In this paper, a novel filtering power divider with external isolation resistors is presented. The proposed power divider can be considered as an integration of a bandpass filter and a Gysel power divider. Based on the circuit topology, a high-order filtering power divider can be easily realized. Odd- and even-mode models are employed to analyze the filtering and power splitting functions. For demonstration, a third-order filtering power divider operating at 1.5 GHz is designed and implemented. The measured results exhibit an isolation between the output ports that is better than 20 dB at around the center frequency.

• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2001.11a
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• pp.123-127
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• 2001

In this paper, prototype high-power-factor single-stage electronic ballast for fluorescent lamps is designed and implemented. A new low cost single stage high power factor electronic ballast for fluorescent lamps is based on integration of two-boost converter and LC type high frequency resonant converter. A ballast is obtained by simple construction, because full bridge rectifier diode is eliminated and simple control circuit is applied. Using two boost converter operating positive and negative half cycle respectively at line frequency (60Hz), operation in discontinuous conduction mode performs high power factor. The experimental results Show the good performance as PF 0.99, $A_{THD}$ 15.4%, and CF 1.65 at Output 63.5W.W.