• Journal of Hydrogen and New Energy
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• v.23 no.5
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• pp.513-520
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• 2012

The electrochemical reaction of refuse derived fuel (RDF) and refuse plastic/paper fuel (RPF) was investigated in the direct carbon fuel cell (DCFC) system. The open circuit voltage (OCV) of RPF was higher than RDF and other coals because of its thermal reactive characteristic under carbon dioxide. The thermal reactivity of fuels was investigated by thermogravimetric analysis method. and the reaction rate of RPF was higher than other fuels. The behavior of all sample's potential was analogous in the beginning region of electrochemical reactions due to similar functional groups on the surface of fuels analyzed by X-ray Photoelectron Spectroscopy experiments. The potential level of RDF and RPF decreased rapidly comparing to coals in the next of the electrochemical reaction because the surface area and pore volume investigated by nitrogen gas adsorption tests were smaller than coals. This characteristic signifies the contact surface between electrolyte and fuel is restricted. The potential of fuels was maintained to the high current density region over 40 $mA/cm^2$ by total carbon component. The maximum power density of RDF and RPF reached up to 45~70% comparing to coal. The obvious improvement of maximum power density by increasing operating temperature was observed in both refuse fuels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.5
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• pp.248-254
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• 2001

The traction power demand highly varies with time and train positions and the traction load is a large-capacity current at single phase converted from 3-phase power system. Subsequently, each phase current converted from 3-phase power system cannot be maintained in balance any longer and thus the traction load can bring about imbalance in three-phase voltage. Therefore, the exact assessment of voltage unbalance must be carried out preferentially as well as load forecast at stages of designing and planning for electric railway system. The evaluation of unbalance voltage in areas, such as electric railway depots should be a prerequisite with more accuracy. The conventional researches on voltage unbalance have dealt with connection schemes of the transformers used in ac AT-fed electric railroads system and induced formulas to briefly evaluate voltage unbalance in the system(3). These formulas are still being used widely due to their easy applicabilities on voltage unbalance evaluation. Meanwhile, they don't take into account detailed characteristics of ac AT-fed electric railroads system, being founded on some assumptions. Accordingly. accuracy still remains in question. This paper proposes a new method to more effectively estimate voltage unbalance index. In this method, numerous diverted circuits in electric railway depots are categorized in three components and each component is defined as a two-port network model. The equivalent circuit for the entire power supply system is also described into a two-port network model by making parallel and/or series connections of these components. Efficiency and accuracy in voltage unbalance calculation as well can be promoted by simplifying the circuits into two-port network models.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.640-645
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• 2012

DC-DC converter and DC-AC inverter in a hybrid electric vehicle (HEV) generate the switching noise. It may be generated by the reverse recovery operation of the power diode in the switching circuit of the converter or the inverter. The shape of the reverse recovery region may be determined by both reverse time and recovery time in the diode. So, in this paper, the frequency spectrum of switching noise was estimated by the shape of the reverse recovery region and compared with the measured results. It shows that the meaningful region of the frequency spectrum is directly related with the reverse time.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.49-53
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• 1999

In this study, the characteristics of the structure of buried type capacitor for RF multi- chip-module are investigated. We developed many kinds of structures to minimize the space of capacitor in module and the value of parastic series inductance without any loss in capacitance, and in this procedure the effect of vias especially position, size, number length are analyzed and optimized. This characteristics of structures are checked through HFSS(high frequency structure simulator) of HP, and the value of parastic series inductance is calculated by equivalent circuit analysis. And ensuing the result of simulation, we made buried type capacitors using LTCC (low temperature cofired ceramic) material. In measurement of this sample, we found out the effective and precise method can be applied to buried type and characteristics of vias and striplines added for measuring are quantified.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.415-420
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• 2005

This paper presents the two lossless auxiliary inductors-assisted voltage source type half bridge (single ended push pull: SEPP) series resonant high frequency inverter for induction heated king roller in copy and printing machines. The simple high-frequency inverter treated here can completely achieve stable zero current soft switching (ZCS) commutation for wide its output power regulation ranges and load variations under its constant high frequency pulse density modulation (PDM) scheme. Its transient and steady state operating principle is originally described and discussed for a constant high-frequency PDM control strategy under a stable ZCS operation commutation, together with its output effective power regulation characteristics-based on the high frequency PDM strategy. The experimental operating performances of this voltage source SEPP ZCS-PDM series resonant high frequency inverter using IGBTs are illustrated as compared with computer simulation results and experimental ones. Its power losses analysis and actual efficiency are evaluated and discussed on the basis of simulation and experimental results. The feasible effectiveness of this high frequency inverter appliance implemented here is proved from the practical point of view.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.2
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• pp.94-98
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• 2007

The fault current limiting characteristics of a flux-lock type superconducting fault current limiter (SFCL) considering hysteresis characteristics of a flux-lock reactor, which is an essential component of the flux-lock type SFCL, were investigated. In the normal state, the hysteresis loss of iron core in the flux-lock type SFCL does not happen due to its winding's structure. From the equivalent circuit for the flux-lock type SFCL and the fault current limiting experiments, the hysteresis curves could be drawn. Through the hysteresis curves together with the fault current level due to the inductance ratio between the primary and the secondary windings, the increase of the number of turns in the secondary winding of the flux-lock type SFCL made the fault current level increase. On the other hand, the saturation of iron core was prevented.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.2
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• pp.829-834
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• 2011

Exposure process is the most important technology to fabricate highly integrated circuit. Up to now, mask type lithography process has been generally used. However, it is not efficient for small quantity and/or frequently changing products. Therefore, maskless lithography technology is raised in exposure process. In this study, relations between multi-beam energy and overlay were analyzed. Exposure experiment of generating pattern was performed. It was from presented scan line by multi- beam simulation. As a result, optimal scan line distance was proposed by simulation, and micro pattern accuracy could be improved by exposure experiment using laser direct imaging system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.9
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• pp.522-529
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• 2002

In this paper, computer simulations of the physical Phenomena occurring in the arc region before and after current zero were carried out to evaluate the thermal recovery characteristics of a Laval nozzle. A commercial CFD program "PHOENICS" is used for the simulation and the user-coded subroutines to consider the arcing phenomena were added to this program by the authors. The computed results were verified by the comparison with the test results presented by the research group of GE Co.(General Electric Company). In order to investigate the state of the arc region after current zero, the simulation was carried out with three steps. They are steady state arc simulation, transient arc simulation before current zero, and transient hot-gas flow simulation after current zero. The semi-experimental arc radiation model is adapted to consider the radiation energy transport and Prandtl's mixing length model is employed as the turbulence model. The electric field and the magnetic field were calculated with the same grid structure used for the simulation of the flow field. The post-arc current was calculated to evaluate the thermal recovery characteristics after current zero. Compared with the results obtained by GE Co., it has been found that the critical RRRV(ratio of rise of recovery voltage) will be determined previously by this study.his study.