• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.56-63
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• 2001

In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.57-63
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• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1250-1254
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• 2007

The multi-resonant(MR) converter has a characteristics that the parasitic components existing in the converter are absorbed into the resonant circuits. The designed MR converter could be got a high efficiency and a high power density because the switching power losses are reduced effectively due to resonant switching circuit. However, the high resonant voltage stress of switching power devices leads to the conduction loss. In this paper, it is proposed the novel alternated(AT) flyback multi-resonant converter to overcome such a drawback. The suggested converter dc input is divided by two series input filter capacitors. The resonant stress voltage is reduced to 2-3 times the input voltage without any complexity and it provides the various circuit schemes in lots of applications. The proposed flyback MR converter is verified through simulation and experiment.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.520-522
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• 2008

A novel two-switch active clamp forward converter suitable for high input voltage applications is proposed. The main advantage of the proposed converter, compared to the conventional active forward converters, is that circuit complexity is reduced and the voltage stress of the main switches is effectively clamped to either the input voltage or the clamping capacitor voltage by two clamping diodes without limiting the maximum duty ratio. Also, the clamping circuit does not include additional active switches, so a low cost can be achieved without degrading the efficiency. Therefore, the proposed converter can feature high efficiency and low cost for high input voltage applications. The operational principles, features, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 200W, 375V input, and 12V output.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1226-1228
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• 2001

In this paper, the modified simulation algorithms of the Auto Transformer (AT) feeding electric train were proposed. To obtain terminal voltage of train by using equivalent circuit of the AT feeding system, the iterative method is proposed for which determine the train voltages. The train voltages are iteratively calculated from the system voltage drop and line impedance. In the case study, the proposed method is verified from actual operation data of the Kwa-Chon line. Also it is verified that the proposed method can be extent to the multi-train simulation tool. The terminal voltage of the multi-train can be calculated by using superposition principle and it is easily applied to the proposed method. Therefore, the proposed method can be a solution for the complexity of the circuit analysis in the existing methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2529-2533
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• 1999

This paper proposes a modified hysteresis current control method based on space vector modulation. The proposed method differs from former works in that it uses effective voltage vectors instead of zero vectors while not significantly increasing the circuit complexity. The circuit uses outer band that is slightly wider than the usual current limit band (inner band) to detect the phase of current command and thereby the region information. The comparator output signals associated with the inner and outer band are used to determine the proper voltage vector that minimizes the current error and number of switching, with simple logic circuitry. The utilization of effective voltage vector is of particular importance when the ac-side emf is relatively large. Both the simulation and experiment show that the proposed method is more effective than the conventional one that uses zero vectors, in reducing the number of switching over a range of ac-side emf variation.