• 제목/요약/키워드: Circuit Complexity

검색결과 241건 처리시간 0.028초

유한체상의 자원과 시간에 효율적인 다항식 곱셈기 (Resource and Delay Efficient Polynomial Multiplier over Finite Fields GF (2m))

  • 이건직
    • 디지털산업정보학회논문지
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    • 제16권2호
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    • pp.1-9
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    • 2020
  • Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

Pipeline 시스템의 Hazard 검출기를 위한 BIST 설계 (BIST Design for Hazard controller in Pipeline System)

  • 이한권;이현룡;장종권
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 컴퓨터소사이어티 추계학술대회논문집
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    • pp.27-30
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    • 2003
  • The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

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유한체 GF(24)를 이용한 GF(216)의 직렬 곱셈기 설계와 이의 C언어 시뮬레이션 ((Design of GF(216) Serial Multiplier Using GF(24) and its C Language Simulation)

  • 신원철;이명호
    • 한국컴퓨터정보학회논문지
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    • 제6권3호
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    • pp.56-63
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    • 2001
  • 본 논문에서는 부분체(24)를 갖는 유한체 GF(216)의 곱셈기를 설계하였다. 이런 설계는 부분체를 이용한 비트 병렬 곱셈기를 사용한 순차 논리 곱셈기를 만들기 위해 사용된다. 부분체 상의 병렬연산기를 사용하여 유한체 GF(216)의 직렬 곱셈기를 설계하면 기존의 직렬 곱셈기보다는 짧은 지연시간을 얻을 수 있으며, 병렬 곱셈기보다는 적은 하드웨어로 구현할 수 있다. 이러한 설계는 유용한 특징을 갖는다. 여기서는 회로 복잡도와 지연시간의 특징을 비교하고 C언어를 이용하여 시뮬레이션 결과를 보였다.

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A 10-bit Current-steering DAC in 0.35-μm CMOS Process

  • Cui, Zhi-Yuan;Piao, Hua-Lan;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제10권2호
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    • pp.44-48
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    • 2009
  • A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

3치 범용 논리 모듈 $U_h$에 의한 빠른 논리 합성 (Fast Synthesis based on Ternary Universal Logic Module $U_h$)

  • 김영건;김종오;김흥수
    • 전자공학회논문지B
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    • 제31B권1호
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    • pp.57-63
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    • 1994
  • The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.

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AT 플라이백 다중공진형 컨버터 동작모드 해석 (Operational Mode Analysis of the AT Flyback Multi-Resonant Converter)

  • 박귀철;김창선
    • 전기학회논문지
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    • 제56권7호
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    • pp.1250-1254
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    • 2007
  • The multi-resonant(MR) converter has a characteristics that the parasitic components existing in the converter are absorbed into the resonant circuits. The designed MR converter could be got a high efficiency and a high power density because the switching power losses are reduced effectively due to resonant switching circuit. However, the high resonant voltage stress of switching power devices leads to the conduction loss. In this paper, it is proposed the novel alternated(AT) flyback multi-resonant converter to overcome such a drawback. The suggested converter dc input is divided by two series input filter capacitors. The resonant stress voltage is reduced to 2-3 times the input voltage without any complexity and it provides the various circuit schemes in lots of applications. The proposed flyback MR converter is verified through simulation and experiment.

A Novel Two-Switch Active Clamp Forward Converter for High Input Voltage Applications

  • Kim, Jae-Kuk;Oh, Won-Sik;Moon, Gun-Woo
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2008년도 하계학술대회 논문집
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    • pp.520-522
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    • 2008
  • A novel two-switch active clamp forward converter suitable for high input voltage applications is proposed. The main advantage of the proposed converter, compared to the conventional active forward converters, is that circuit complexity is reduced and the voltage stress of the main switches is effectively clamped to either the input voltage or the clamping capacitor voltage by two clamping diodes without limiting the maximum duty ratio. Also, the clamping circuit does not include additional active switches, so a low cost can be achieved without degrading the efficiency. Therefore, the proposed converter can feature high efficiency and low cost for high input voltage applications. The operational principles, features, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 200W, 375V input, and 12V output.

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AT 급전계통 전기철도 해석 알고리즘 연구 (A study on algorithm of AT feeding systems)

  • 추동욱;김재철;김낙경
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 하계학술대회 논문집 B
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    • pp.1226-1228
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    • 2001
  • In this paper, the modified simulation algorithms of the Auto Transformer (AT) feeding electric train were proposed. To obtain terminal voltage of train by using equivalent circuit of the AT feeding system, the iterative method is proposed for which determine the train voltages. The train voltages are iteratively calculated from the system voltage drop and line impedance. In the case study, the proposed method is verified from actual operation data of the Kwa-Chon line. Also it is verified that the proposed method can be extent to the multi-train simulation tool. The terminal voltage of the multi-train can be calculated by using superposition principle and it is easily applied to the proposed method. Therefore, the proposed method can be a solution for the complexity of the circuit analysis in the existing methods.

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디지털 CMOS 회로의 Multi-Level Test를 위한 범용 Test Set 생성 (Universal Test Set Generation for Multi-Level Test of Digital CMOS Circuits)

  • Dong Wook Kim
    • 전자공학회논문지A
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    • 제30A권2호
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    • pp.63-75
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    • 1993
  • As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

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개선된 공간벡터형 히스테리시스 전류제어기법 (Modified Space-Vector Modulation Hysteresis Current Control Method)

  • 정안식;박기원;정승기
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 F
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    • pp.2529-2533
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    • 1999
  • This paper proposes a modified hysteresis current control method based on space vector modulation. The proposed method differs from former works in that it uses effective voltage vectors instead of zero vectors while not significantly increasing the circuit complexity. The circuit uses outer band that is slightly wider than the usual current limit band (inner band) to detect the phase of current command and thereby the region information. The comparator output signals associated with the inner and outer band are used to determine the proper voltage vector that minimizes the current error and number of switching, with simple logic circuitry. The utilization of effective voltage vector is of particular importance when the ac-side emf is relatively large. Both the simulation and experiment show that the proposed method is more effective than the conventional one that uses zero vectors, in reducing the number of switching over a range of ac-side emf variation.

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