• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1899-1907
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• 2013

This paper presents an efficient defect detection and classification system based on reference image for COF (Chip-on-Film) which encounters fatal defects after ultra fine pattern fabrication. These defects include typical ones such as open, mouse bite (near open), hard short and soft short. In order to detect these defects, conventionally it needs visual examination or electric circuits. However, these methods requires huge amount of time and money. In this paper, based on reference image, the proposed system detects fatal defect and efficiently classifies it to one of 4 types. The proposed system includes the preprocessing of the test image, the extraction of ROI, the analysis of local binary pattern and classification. Through simulations with lots of sample images, it is shown that the proposed system is very efficient in reducing huge amount of time and money for detecting the defects of ultra fine pattern COF.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1149-1152
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• 2003

Now a days, many different kinds of display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), and Liquid Crystal On Silicon (LCOS) are designed. And these display technologies will be used in many application products like High Definition Televisions (HDTVs) or mobile devices. In this paper, pattern generation circuit for display test is proposed. The proposed circuit will be embedded in the control circuit of display chip. Two differenct kinds of patterns is generated by the circuit. One is block pattern for color test, and the other is line pattern for pixel test. The shape of test pattern is determined by the values of registers in pattern generation circuit. The circuit is designed using Verilog HDL RTL code.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of Welding and Joining
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• v.25 no.2
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• pp.76-81
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• 2007

Solder bumps have been used to interconnect the chip and substrate, and the size of the solder bump decreases below $100{\mu}m$ to accommodate higher packaging density. In order to fabricate solder bumps, a mold to chip transfer process is suggested in this work. Since the thin stainless steel mold is not wet by the solder, the molten solder is forced to fill the mold cavities with ultrasonic vibration. The solders within the mold cavities are transferred to the Cu pads on the polyimide film through reflow soldering.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.3 no.2
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• pp.63-68
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• 1989

This paper discussed the Multi-PAM inverter for static power supply design. The controller part composed of one-chip microcomputer obtained control pattern simply. The configuration of termination part was composed of double bridge inverter and three-phase, three-winding transformer. The output waveforms using a controller and transformers synthesized the multi-PAM wave form by a voltage level of 22 steps per one-cycle. The output waveforms using the Low Pass Filter approximated to the sine wave.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.128-139
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• 1996

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

• Korean Journal of Biological Psychiatry
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• v.8 no.2
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• pp.203-207
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• 2001

The genome sequencing project has generated and will continue to generate enormous amounts of sequence data including 5 eukaryotic and about 60 prokaryotic genomes. Given this ever-increasing amounts of sequence information, new strategies are necessary to efficiently pursue the next phase of the genome project-the elucidation of gene expression patterns and gene product function on a whole genome scale. In order to assign functional information to the genome sequence, DNA chip(or gene microarray) technology was developed to efficiently identify the differential expression pattern of independent biological samples. DNA chip provides a new tool for genome expression analysis that may revolutionize many aspects of biotechnology including new drug discovery and disease diagnostics.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.739-741
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• 1993

This paper deals with the Improvement of inverter output waveform with space vector modulation using the DSP-chip. The proposed scheme can be considered as a alternative of the conventional, subharmonic method. This scheme features a maximum output voltage that is 15% greater. The number of switchings is also 30% less than the one obtained by subharmonic modulation method(SHM) A performance function(PF) which is the time integral function of the inverter output voltage is introduced in this paper. An optimal PWM pattern is obtained by minimizing the distortion factor of performance function. The experiment was carried out with an TMS320C25.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.197-199
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• 2002

This paper describes the effects of chip arrangement configurations and the dimension of a reflecting cup upon the light output characteristics of a white lamp composed of RGB LED chips. As a result of simulation, the shorter distance between adjacent chips leads to a relative decrease in the light output efficiency due to inter-chip absorption of quanta, but rather uniform color mixing is expected. Among the factors of designing a reflecting cup it is the tilt angle of the cup wall that plays a determining role upon the variation of the light distribution. The light distribution shows a sudden change of pattern from Lambertian to Batwing at about $35^{\circ}{\sim}40^{\circ}$ of tilt angle in case of a silver-coated wall cup.