• 제목/요약/키워드: Chip pattern

검색결과 311건 처리시간 0.03초

차영상을 이용한 실시간 TCP/COF 검사 시스템 개발 (Development of Real-Time TCP/COF Inspection System using Differential Image)

  • 이상원;최환용;이대종;전명근
    • 한국지능시스템학회논문지
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    • 제22권1호
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    • pp.87-93
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    • 2012
  • 본 논문에서는 TCP/COF의 불량패턴 검출 알고리즘을 제안하고 실시간 검사 시스템을 구현하였다. TCP/COF는 마이크로미터 단위의 패턴 굵기를 갖는 관계로 검사를 위해서는 작업자가 고성능 현미경을 보며 전수 검사 해야 하는 어려움이 있다. 이에 본 연구에서는 작업자로 하여금 모니터를 보면서 검사시스템이 검출해내는 불량에 대해서 검사할 수 있는 시스템을 제안하였다. 검사 알고리즘은 기준 영상과 검사 영상간의 패턴 비교 방법에 의해 수행된다. TCP/COF의 특성에 맞는 고성능 카메라 및 조명시스템을 구현하기 위하여 카메라의 종류와 조명의 형태 및 광원에 따른 다양한 실험을 수행하였다. 실험결과 구현된 검사 시스템은 TCP/COF 필름의 불량 위치를 작업자에게 정확하게 알려줌을 확인할 수 있었다.

HD 영상의 실시간 얼굴 검출을 위한 LBP 연산의 하드웨어 설계 (Hardware Design of LBP Operation for Real-time Face Detection of HD Images)

  • 노현진;김태완;정연모
    • 대한전자공학회논문지SD
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    • 제48권10호
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    • pp.67-71
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    • 2011
  • 디지털 도어락, 디지털 카메라, 비디오 감시 시스템 등에서 사용되는 기존의 얼굴 검출 시스템은 비교적 낮은 해상도의 영상 처리를 사용하고 있으며 이를 위해서 소프트웨어 기반의 구현을 하고 있다. 하지만 이 경우에는 높은 해상도를 위한 얼굴 검출이 어려울 뿐만 아니라 수행해야할 영산 처리 양이 많기 때문에 실시간으로 얼굴을 검출하는데 어려움이 있다. 실시간 임베디드 시스템에서 HD(High Definition) 영상을 위한 효과적인 얼굴 검출을 위해서는 하드웨어적인 접근이 필요하다. 이에 본 논문에서는 얼굴 검출을 위해 사용되는 전처리 과정 중에 하나이며 처리시간이 많이 소요되는 국부 이진 패턴(LBP, Local Binary Pattern) 연산을 하드웨어 구조를 제시하고 설계했다. 그리고 제시한 하드웨어 구조를 FPGA(Field Programmable Gate Array) 칩을 통해서 구현 및 검증을 통해 고해상도 HD급 영상에서 효율적인 얼굴 검출이 가능 한 것을 확인했다.

능동 폴리머 펜 어래이를 이용한 미세 패터닝 (Micro Patterning Using Active Polymer Pen Array)

  • 한윤수;홍지화
    • 한국전기전자재료학회논문지
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    • 제26권12호
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    • pp.853-857
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    • 2013
  • We design, develope and test a parallel active polymer pen lithography (PPL) device, which consists of individually addressable elastomeric probe tips. The PPL array chip is fabricated using soft lithography method with polydimethylsiloxane (PDMS) material. Individual probe can be pneumatically actuated via a computer controlled interface. We demonstrate parallel writing with 16 individually addressed pens, with each pen producing a different pattern in the same run. The largest proof-of-concept array fabricated is $4{\times}4$ with a spacing of $250{\mu}m$ in both x and y axes.

센서 기반의 디바이스 DNA 기술 동향 (Trends in Device DNA Technology Trend for Sensor Devices)

  • 김주한;이상재;오미경;강유성
    • 전자통신동향분석
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    • 제35권1호
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    • pp.25-33
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    • 2020
  • Just as it is possible to distinguish people by using physical features, such as fingerprints, irises, veins, and faces, and behavioral features, such as voice, gait, keyboard input pattern, and signatures, the an IoT device includes various features that cannot be replicated. For example, there are differences in the physical structure of the chip, differences in computation time of the devices or circuits, differences in residual data when the SDRAM is turned on and off, and minute differences in sensor sensing results. Because of these differences, Sensor data can be collected and analyzed, based on these differences, to identify features that can classify the sensors and define them as sensor-based device DNA technology. As Similar to the biometrics, such as human fingerprints and irises, can be authenticatedused for authentication, sensor-based device DNA can be used to authenticate sensors and generate cryptographic keys that can be used for security.

출력단 ESD 보호회로의 설계 및 그 전기적 특성에 관한 연구 (A Study on the Design of the Output ESD Protection Circuits and their Electrical Characteristics)

  • 김흥식;송한정;김기홍;최민성;최승철
    • 전자공학회논문지A
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    • 제29A권11호
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    • pp.97-106
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    • 1992
  • In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

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하반신마비 환자의 보행기능 제어를 위한 FES하드웨어 시스템 설계에 관한 연구 (A Study on Design of FES Hardware System for Walking of Paraplegics)

  • 김근섭;김종원
    • 대한의용생체공학회:의공학회지
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    • 제12권1호
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    • pp.1-7
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    • 1991
  • This paper describes and discusses the employment of HMG pattern analysis to provide upper-motor-neuron paraplegics with patient-responsive control of FES ( functional electrical stimulation) for the purpose of walker-supported walking. The use of above-lesion EMG signals as a solution to the control problem is considered. The AR(autoregressive)parameters are identified by time-varying nonstationary Kalman filler algorithm using DSP chip and classified by fuzzy theory. The control and stimuli part of the below-lesion are based on micro-processor(8031). The designed stimulator is a 4-channel version. The experiments described above have only attempted to discriminate between standing function and sit-down function A further advantge of the this system Is applied for motor rehabilitation of social readaption of paralyzed humans.

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가변 위상각제어에 의한 에너지절감형 단상유도전동기에 관한 연구 (A Study on the Energy Saving SPIM Using Variable Phase Angle Control)

  • 박수강;백형래;이상일;임양수;최낙일
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1999년도 전력전자학술대회 논문집
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    • pp.522-525
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    • 1999
  • This paper describes a simple but effective method for energy saving of ac motors having a widely variable load. The proposed method is based on an optimal efficiency control which is operated by voltage-current pattern such as to maintain the maximum efficiency on the efficiency-output characteristics of the motor, in voltage control with triac. In this paper, authors present the experimental results of the SPIM under controlling of current of main and auxiliary winding by using a one chip microcontroller. Experiments are focused on a capacitor stating single phase induction motor the optimal energy saving are proved by the proposed method.

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기하학적 왜곡을 고려한 카메라 모델링 및 머신비젼 시스템에 관한 연구 (A Study on Machine Vision System and Camera Modeling with Geometric Distortion)

  • 계중읍
    • 한국생산제조학회지
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    • 제7권4호
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    • pp.64-72
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    • 1998
  • This paper a new approach to the design of machine vision technique with a camera modeling that accounts for major sources of geometric distortion, namely, radial, decentering, and thin prism distortion. Radial distortion causes an inward or outward displacement of a given image point from its ideal location. Actual optical systems are subject to various degrees of decentering , that is , the optical centers of lens design and manufacturing as well as camera assembly. It is our propose to develop the vision system for the pattern recognition and the automatic test of parts and to apply the line of manufacturing. The performance of proposed vision system is illustrated by simulation and experiment.

Laser Drilling of High-Density Through Glass Vias (TGVs) for 2.5D and 3D Packaging

  • Delmdahl, Ralph;Paetzel, Rainer
    • 마이크로전자및패키징학회지
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    • 제21권2호
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    • pp.53-57
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    • 2014
  • Thin glass (< 100 microns) is a promising material from which advanced interposers for high density electrical interconnects for 2.5D chip packaging can be produced. But thin glass is extremely brittle, so mechanical micromachining to create through glass vias (TGVs) is particularly challenging. In this article we show how laser processing using deep UV excimer lasers at a wavelength of 193 nm provides a viable solution capable of drilling dense patterns of TGVs with high hole counts. Based on mask illumination, this method supports parallel drilling of up over 1,000 through vias in 30 to $100{\mu}m$ thin glass sheets. (We also briefly discuss that ultrafast lasers are an excellent alternative for laser drilling of TGVs at lower pattern densities.) We present data showing that this process can deliver the requisite hole quality and can readily achieve future-proof TGV diameters as small $10{\mu}m$ together with a corresponding reduction in pitch size.

정전용량 주사형 데시미크론 현미경의 구현 (Implementation of scanning capacitance decimicron microscope)

  • 권영도;이주신
    • 전자공학회논문지S
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    • 제35S권3호
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    • pp.120-130
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    • 1998
  • In this study, we implemented a scanning capacitance decimicron micorscope(SCdM) which scans a surface of the object mechanically in two or two point five dimensions with a stylus of size 0.2.mu.m. X-Y stage and stylus driving method are used as the scanning method, and VHD disk plate and IC chip are used as the object. Experimenal resutl of these object show that SCdM obtain 0.1.mu.m resolution power which exceeds that of optical microscope, and this microscope will be used as a powerful tool for inspecting ULSI pattern or biological data as a decimicron mcirocope which zoom a function of optical microscope and guide STM. The experimental system is composed of a VHD video disk method which captures the capacitance changes of the video disk suface and converts it into video signal.

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