• 제목/요약/키워드: Chip on chip technology

검색결과 1,650건 처리시간 0.034초

자동차 글라스 조립 자동화설비를 위한 FPGA기반 실러 도포검사 비전시스템 개발 (Development of an FPGA-based Sealer Coating Inspection Vision System for Automotive Glass Assembly Automation Equipment)

  • 김주영;박재률
    • 센서학회지
    • /
    • 제32권5호
    • /
    • pp.320-327
    • /
    • 2023
  • In this study, an FPGA-based sealer inspection system was developed to inspect the sealer applied to install vehicle glass on a car body. The sealer is a liquid or paste-like material that promotes adhesion such as sealing and waterproofing for mounting and assembling vehicle parts to a car body. The system installed in the existing vehicle design parts line does not detect the sealer in the glass rotation section and takes a long time to process. This study developed a line laser camera sensor and an FPGA vision signal processing module to solve this problem. The line laser camera sensor was developed such that the resolution and speed of the camera for data acquisition could be modified according to the irradiation angle of the laser. Furthermore, it was developed considering the mountability of the entire system to prevent interference with the sealer ejection machine. In addition, a vision signal processing module was developed using the Zynq-7020 FPGA chip to improve the processing speed of the algorithm that converted the profile to the sealer shape image acquired from a 2D camera and calculated the width and height of the sealer using the converted profile. The performance of the developed sealer application inspection system was verified by establishing an experimental environment identical to that of an actual automobile production line. The experimental results confirmed the performance of the sealer application inspection at a level that satisfied the requirements of automotive field standards.

X-대역 응용을 위한 GaN 기반 저잡음 증폭기 MMIC (GaN-based Low Noise Amplifier MMIC for X-band Applications)

  • 임병옥;고주석;김성찬
    • 전기전자학회논문지
    • /
    • 제28권1호
    • /
    • pp.33-37
    • /
    • 2024
  • 본 논문에서는 0.25 ㎛ 게이트 길이를 갖는 GaN HEMT 기술을 사용하여 개발한 X-대역 저잡음 증폭기 MMIC의 특성을 기술한다. 개발된 GaN 기반 X-대역 저잡음 증폭기 MMIC는 9 GHz ~ 10 GHz의 동작 주파수 대역에서 22.75 dB ~ 25.14 dB의 소신호 이득과 1.84 dB ~ 1.94 dB의 잡음지수 특성을 나타내었다. 입력 반사 손실 특성과 출력 반사 손실 특성은 각각 -11.36 dB ~ -24.49 dB, -11.11 dB ~ -17.68 dB를 얻었으며 40 dBm (10 W)의 입력 전력에 성능 열화 없이 정상적으로 동작하였다. MMIC의 크기는 3.67 mm × 1.15 mm이다. 개발된 GaN 기반 저잡음 증폭기 MMIC는 X-대역의 다양한 응용에 적용 가능하다.

드릴공구의 이종질화막상 DLC 희생층 적용을 통한 공구 수명 개선 연구 (A Study on the Improvement of Tool's Life by Applying DLC Sacrificial Layer on Nitride Hard Coated Drill Tools)

  • 강용진;김도현;장영준;김종국
    • 한국표면공학회지
    • /
    • 제53권6호
    • /
    • pp.271-279
    • /
    • 2020
  • Non-ferrous metals, widely used in the mechanical industry, are difficult to machine, particularly by drilling and tapping. Since non-ferrous metals have a strong tendency to adhere to the cutting tool, the tool life is greatly deteriorated. Diamond-like carbon (DLC) is one of the promising candidates to improve the performance and life of cutting tool due to their low frictional property. In this study, a sacrificial DLC layer is applied on the hard nitride coated drill tool to improve the durability. The DLC coatings are fabricated by controlling the acceleration voltage of the linear ion source in the range of 0.6~1.8 kV. As a result, the optimized hardness(20 GPa) and wear resistance(1.4 x 10-8 ㎣/N·m) were obtained at the 1.4 kV. Then, the optimized DLC coating is applied as an sacrificial layer on the hard nitride coating to evaluate the performance and life of cutting tool. The Vickers hardness of the composite coatings were similar to those of the nitride coatings (AlCrN, AlTiSiN), but the friction coefficients were significantly reduced to 0.13 compared to 0.63 of nitride coatings. The drilling test were performed on S55C plate using a drilling machine at rotation speed of 2,500 rpm and penetration rate of 0.25 m/rev. The result showed that the wear width of the composite coated drills were 200 % lower than those of the AlCrN, AlTiSiN coated drills. In addition, the cutting forces of the composite coated drills were 13 and 15 % lower than that of AlCrN, AlTiSiN coated drills, respectively, as it reduced the aluminum clogging. Finally, the application of the DLC sacrificial layer prevents initial chipping through its low friction property and improves drilling quality with efficient chip removal.

ZnO-Zn2BiVO6-Mn3O4 바리스터의 미세구조와 전기적 특성 (Microstructure and Electrical Properties of ZnO-Zn2BiVO6-Mn3O4 Varistor)

  • 홍연우;하만진;백종후;조정호;정영훈;윤지선
    • 한국전기전자재료학회논문지
    • /
    • 제31권5호
    • /
    • pp.313-319
    • /
    • 2018
  • This study introduces a new investigation report on the microstructural and electrical property changes of $ZnO-Zn_2BiVO_6-Mn_3O_4$ (ZZMn), where 0.33 mol% of $Mn_3O_4$ and 0.5 mol% of $Zn_2BiVO_6$ were added to ZnO (99.17 mol%) as liquid phase sintering aids. $Zn_2BiVO_6$ contributes to the decrease of sintering temperatures by up to $800^{\circ}C$, and segregates its particles at the grain boundary, while $Mn_3O_4$ enhances ${\alpha}$, the nonlinear coefficient, of varistor properties up to ${\alpha}=62$. In comparison, when the sintering temperature is increased from $800^{\circ}C$ to $1,000^{\circ}C$, the resistivity of ZnO grains decreases from $0.34{\Omega}cm$ to $0.16{\Omega}cm$, and the varistor property degrades. Oxygen vacancy ($V_o^{\bullet}$) (P1, 0.33~0.36 eV) is formed as a dominant defect. Two different kinds of grain boundary activation energies of P2 (0.51~0.70 eV) and P3 (0.70~0.93 eV) are formed according to different sintering temperatures, which are tentatively attributed to be $ZnO/Zn_2BiVO_6$-rich interface and ZnO/ZnO interface, respectively. Accordingly, this study introduces a progressive method of manufacturing ZnO chip varistors by way of sintering ZZMn-based varistor under $900^{\circ}C$. However, to procure a higher reliability, an in-depth study on the multi-component varistors with double-layer grain boundaries should be executed.

전송선로에 적용한 Low-k 고분자 복합 잉크 개발 (Low-k Polymer Composite Ink Applied to Transmission Line)

  • 남현진;정재웅;서덕진;김지수;유종인;박세훈
    • 마이크로전자및패키징학회지
    • /
    • 제29권2호
    • /
    • pp.99-105
    • /
    • 2022
  • 칩사이즈가 작아짐에 따라 선폭 또한 미세화되면서 인터커넥션의 밀집정도가 증가하고 있다. 그로 인해 캐패시터 층과 전기전도층의 저항 차이로 인해 RC delay가 문제되고 있다. 이를 해결하기 위해서는 높은 전기전도도의 전극과 낮은 유전율의 유전체 개발이 요구된다. 본 연구에서는 PCB (Print Circuit Board)의 회로를 외부요인으로부터 보호하는 상용 PSR (photo solder resist)과 우수한 내열 및 저유전 특성을 보유한 PI (polyimide)를 혼합하여 저유전체 잉크 개발을 진행하였다. 그 결과 PSR과 PI를 10:3으로 혼합한 잉크가 가장 우수한 결과를 보였으며 20 GHz와 28 GHz에서 각각 유전 상수 약 2.6, 2.37을 보였고, 유전손실은 약 0.022, 0.016으로 측정되었다. 차후 어플리케이션 적용 가능성 검증을 위해 테프론에 제작된 다양한 선폭의 전송선로에 평가하였으며 그 결과, PSR만 사용했을 때보다 PI와 혼합한 저유전체 잉크를 사용한 전송선로의 손실이 S21에서 평균 0.12 dB 덜 감소한 결과를 보였다.

양액재배용 목재고형배지의 이화학적 특성과 작물생육 특성 (Physiochemical Properties and Plant Growth of The Hydroponic Substrate Using Waste Wood Chip)

  • 권구중;양지욱;박효섭;조준형;김대영
    • Journal of the Korean Wood Science and Technology
    • /
    • 제43권3호
    • /
    • pp.400-409
    • /
    • 2015
  • 본 연구는 폐목재칩, 라디에타파인칩 그리고 폐목재칩을 매트타입으로 제조한 것을 이용한 양액재배용 고형배지에 대한 특성과 엽채류를 이용한 작물생육발달특성을 검토하였다. 가비중은 폐목재칩이 $0.20g/cm^2$, 라디에타 파인칩이 $0.16g/cm^2$였고, 수분보유율은 폐목재칩과 라디에타파인칩으로 제조한 목재고형배지가 대조구인 암면과 코코피트 배지보다 낮았고, 매트타입의 배지가 가장 낮았다. 폐목재 고형배지는 pH 6.59, 전기전도도 6.76 dS/m, 총질소함량 0.50%, 탄질율 113%, 인산(P)함량 10.1 ppm, 카리(K) 77 ppm, 칼슘(Ca)성분 531 ppm, 마그네슘(Mg) 49 ppm, 나트륨(Na) 96 ppm으로 구성되었다. 라디에타파인 고형배지는 pH 5.29, 전기전도도 4.49 dS/m, 총질소함량 0.32%, 탄질율 180%, 인산(P)함량 6.4 ppm, 카리(K) 83 ppm, 칼슘(Ca)성분 97 ppm, 마그네슘(Mg) 29 ppm, 나트륨(Na) 59 ppm으로 구성되었다. 매트형태의 배지를 제외한 목재고형배지의 작물생육발달특성은 암면배지와 코코피트 배지와 유사한 경향을 보여주었다. 이상의 결과에서 폐목재자원을 이용한 유기고형배지는 기존의 배지인 암면배지와 코코피트 배지를 대체할 수 있는 고형배지로서의 가능성을 시사하였다.

IoT Network에서 위치 인식을 위한 가중치 방식의 최대우도방법을 이용한 하드웨어 위치인식엔진 개발 연구 (A Hardwired Location-Aware Engine based on Weighted Maximum Likelihood Estimation for IoT Network)

  • 김동순;박현문;황태호;원광호
    • 전자공학회논문지
    • /
    • 제53권11호
    • /
    • pp.32-40
    • /
    • 2016
  • 센서네트워크 센서노드의 위치정보는 기본적으로 센싱 데이터가 얻어진 위치를 알려주는 목적으로 사용되며 Context 기반 고차원 서비스를 제공하기 위한 가장 중요한 정보중 하나이다. 센서네트워크상에서 위치인식을 위해 다양한 방법들이 연구되고 제안되어 왔으며, 이러한 방법 중에 IEEE 802.15.4 센서네트워크의 물리 계층과 매체 접근 계층을 이용한 위치인식 방법에 관한 연구방법이 크게 대두되고 있다. IEEE 802.15.4 프로토콜은 장치간의 저가격, 저속의 무선 통신을 지향하기 때문에 구현에 있어서 고도화된 최적화가 중요한 요구사항이라 할 수 있다. 하지만 수신 신호의 세기를 가지고 센서 노드들의 위치를 계산하는 방법은 최적화 문제의 해를 구하기 위한 과정이기 때문에 많은 연산 량이 필요로 하게 되고, IEEE802.15.4를 지원하는 System-On-a-Chip (SoC)의 경우 8비트 마이크로 컨트롤러기반으로 설계되어 있다는 점을 고려하면, IEEE802.15.4 기반의 위치 인식 서비스를 위해서는 하드웨어에 기반을 둔 위치 인식 엔진의 필요성이 무엇보다 중요하다. 본 논문은 IEEE 802.15.4 물리계층에 기반을 둔 가중치 기반의 최대우도방법 위치인식기 하드웨어 구현에 관해 제안하고자 한다. 테스트 베드를 이용한 필드테스트 결과 제안하는 하드웨어 기반 가중치 방식의 위치 인식방법은 정확도에서 10% 정도의 개선과 함께 내장 마이크로 컨트롤러의 연산량 및 메모리 액세스를 30% 정도 감소시켜 시스템 전원소모를 줄일 수 있는 결과를 얻을 수 있었다.

Reduction of slaughter age of Hanwoo steers by early genotyping based on meat yield index

  • Jeong, Chang Dae;Islam, Mahfuzul;Kim, Jong-Joo;Cho, Yong-Il;Lee, Sang-Suk
    • Asian-Australasian Journal of Animal Sciences
    • /
    • 제33권5호
    • /
    • pp.770-777
    • /
    • 2020
  • Objective: This study was conducted to determine early hereditary endowment to establish a short-term feeding program. Methods: Hanwoo steers (n = 140) were equally distributed into four groups (35/group) based on genetic meat yield index (MYI) viz. the greatest, great, low, and the lowest at Jukam Hanwoo farm, Goheung. All animals were fed in group pens (5 animals/pen) with similar feed depending on the growth stage. Rice straw was provided ad libitum, whereas concentrate was fed at 5.71 kg during the growing period (6 to 13 mo) and 9.4 kg during the fattening period (13 to 28 mo). Body weight (BW) was measured at two-month intervals, whereas carcass weight was determined at slaughtering at about 31 months of age. The Affymetrix Bovine Axiom Array 640K single nucleotide polymorphism (SNP) chip was used to determine the meat quantity-related gene in the blood. Results: After 6 months, the highest (p<0.05) BW was observed in the greatest MYI group (190.77 kg) and the lowest (p<0.05) in the lowest MYI group (173.51 kg). The great MYI group also showed significantly (p<0.05) higher BW than the lowest MYI group. After 16 and 24 months, the greatest MYI group had the highest BW gain (p<0.05) and were therefore slaughtered the earliest. Carcass weight was significantly (p<0.05) higher in the greatest and the great MYI groups followed by the low and the lowest MYI groups. Back-fat thickness in the greatest MYI group was highly correlated to carcass weight and marbling score. The SNP array analysis identified the carcass-weight related gene BTB-01280026 with an additive effect. The steers with the allele increasing carcass weight had heavier slaughter weight of about 12 kg. Conclusion: Genetic MYI is a potential tool for calf selection, which will reduce the slaughter age while simultaneously increasing carcass weight, back-fat thickness, and marbling score.

Ni/Au 및 OSP로 Finish 처리한 PCB 위에 스크린 프린트 방법으로 형성한 Sn-37Pb, Sn-3.5Ag 및 Sn-3.8Ag-0.7Cu 솔더 범프 계면 반응에 관한 연구 (Studies on the Interfacial Reaction of Screen-Printed Sn-37Pb, Sn-3.5Ag and Sn-3.8Ag-0.7Cu Solder Bumps on Ni/Au and OSP finished PCB)

  • 나재웅;손호영;백경욱;김원회;허기록
    • 한국재료학회지
    • /
    • 제12권9호
    • /
    • pp.750-760
    • /
    • 2002
  • In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn-3.8Ag-0.7Cu were screen printed on both electroless Ni/Au and OSP metal finished micro-via PCBs (Printed Circuit Boards). The interfacial reaction between PCB metal pad finish materials and solder materials, and its effects on the solder bump joint mechanical reliability were investigated. The lead free solders formed a large amount of intermetallic compounds (IMC) than Sn-37Pb on both electroless Ni/Au and OSP (Organic Solderabilty Preservatives) finished PCBs during solder reflows because of the higher Sn content and higher reflow temperature. For OSP finish, scallop-like $Cu_{6}$ /$Sn_{5}$ and planar $Cu_3$Sn intermetallic compounds (IMC) were formed, and fracture occurred 100% within the solder regardless of reflow numbers and solder materials. Bump shear strength of lead free solders showed higher value than that of Sn-37Pb solder, because lead free solders are usually harder than eutectic Sn-37Pb solder. For Ni/Au finish, polygonal shaped $Ni_3$$Sn_4$ IMC and P-rich Ni layer were formed, and a brittle fracture at the Ni-Sn IMC layer or the interface between Ni-Sn intermetallic and P-rich Ni layer was observed after several reflows. Therefore, bump shear strength values of the Ni/Au finish are relatively lower than those of OSP finish. Especially, spalled IMCs at Sn-3.5Ag interface was observed after several reflow times. And, for the Sn-3.8Ag-0.7Cu solder case, the ternary Sn-Ni-Cu IMCs were observed. As a result, it was found that OSP finished PCB was a better choice for solders on PCB in terms of flip chip mechanical reliability.

ZnO-Co3O4-Cr2O3-La2O3 세라믹스의 결함과 입계 특성에 미치는 CaCO3의 영향 (Effects of CaCO3 on the Defects and Grain Boundary Properties of ZnO-Co3O4-Cr2O3-La2O3 Ceramics)

  • 홍연우;하만진;백종후;조정호;정영훈;윤지선
    • 한국전기전자재료학회논문지
    • /
    • 제31권5호
    • /
    • pp.307-312
    • /
    • 2018
  • Liquid phases in ZnO varistors cause more complex phase development and microstructure, which makes the control of electrical properties and reliability more difficult. Therefore, we have investigated 2 mol% $CaCO_3$ doped $ZnO-Co_3O_4-Cr_2O_3-La_2O_3$ (ZCCLCa) bulk ceramics as one of the compositions without liquid phase sintering additive. The results were as follows: when $CaCO_3$ is added to ZCCLCa ($644{\Omega}cm$) acting as a simple ohmic resistor, CaO does not form a secondary phase with ZnO but is mostly distributed in the grain boundary and has excellent varistor characteristics (high nonlinear coefficient ${\alpha}=78$, low leakage current of $0.06{\mu}A/cm^2$, and high insulation resistance of $1{\times}10^{11}{\Omega}cm$). The main defects $Zn_i^{{\cdot}{\cdot}}$ (AS: 0.16 eV, IS & MS: 0.20 eV) and $V_o^{\bullet}$ (AS: 0.29 eV, IS & MS: 0.37 eV) were found, and the grain boundaries had 1.1 eV with electrically single grain boundary. The resistance of each defect and grain boundary decreases exponentially with increasing the measurement temperature. However, the capacitance (0.2 nF) of the grain boundary was ~1/10 lower than that of the two defects (~3.8 nF, ~2.2 nF) and showed a tendency to decrease as the measurement temperature increased. Therefore, ZCCLCa varistors have high sintering temperature of $1,200^{\circ}C$ due to lack of liquid phase additives, but excellent varistor characteristics are exhibited, which means ZCCLCa is a good candidate for realizing chip type or disc type commercial varistor products with excellent performance.