• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.05a
• /
• pp.165-168
• /
• 2002

본 연구에서는 칩인덕터 코어 소재로 사용되는 (NiCuZn)-ferrite를 습식합성법을 이용하여 나노크기의 초미세 분말을 합성하였으며, 합성된 (ZiCuZn)-ferrite 의 제조공정 및 전파기적 특성에 관하여 고찰하였다. 조성은 (N $i_{0.4-x}$C $u_{x}$Z $n_{0.6}$)$_{1+w}$ (F $e_2$ $O_4$)$_{1-w}$에서 x의 값을 0.05~0.25 범위로 변화시켰으며, w 값은 0.03으로 고정하였다. 소결은 8$50^{\circ}C$에서 9$50^{\circ}C$의 범위에서 진행하였다. 나노크기의(NiCuZn)-ferrite를 사용함으로서 시약급 원료로 제조된 것보다 소결온도를 낮출 수 있었고, 밀도가 높은 페라이트 소결체를 얻을 수 있었다. 또한 초투자율, 품질계수 등 전자기적 특성이 우수하게 나타났다. 그 밖에 습식합성법으로 합성한 (NiCuZn)-ferrite 의 결정성, 미세구조 등을 XRD, SEM 을 이용하여 고찰하였다.하였다.다.

• Proceedings of the KIEE Conference
• /
• 2009.04b
• /
• pp.152-155
• /
• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.204-207
• /
• 2000

In this paper, we have studied the effect of doped with B-Bi-Zn on properties (microstructure, density, shrinkage, permeability as a function of frequency, etc.) of hexagonal-ferrite for high frequency chip-inductor material about several GHz. The permeability were analyzed by impedance analyzer(100 kHz~40 MHz) and network analyzer(30 MHz~3 GHZ). As a result of the characteristics, the B-Bi-Zn glass ceramic was used to lower the sintering temperature for additive as a function of frequency from 100 kHz to 1.8 GHz showed constant tends. The maximum imaginary value of complex permeability was observed near the resonance frequency of 2 GHz.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2008.06a
• /
• pp.96-97
• /
• 2008

• Journal of IKEEE
• /
• v.11 no.4
• /
• pp.145-151
• /
• 2007

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss ${Al_2}{O_3}$ core material were investigated. The size of the chip inductors fabricated in this work were $0.86{\times}0.46{\times}0.45m^3$, $1.5{\times}1.0{\times}0.7m^3$, $2.1{\times}1.5{\times}1.0m^3$, and $2.4{\times}2.0{\times}1.4m^3$ and copper (Cu) wire with $27{\sim}40{\mu}m$ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 13 to 100nH and exhibit the self-resonant frequency (SRF) of 6.4 to 1.1GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 50 to 80 in the frequency range of 300MHz to 1.3GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.5
• /
• pp.509-516
• /
• 2004

High-performance Si integrated passive process was developed using thick oxidation process and Cu-BCB process. This passive process leads to low-cost and high-quality RF module with a small form factor. The fabricated spiral inductor with 225 um inner diameter and 2.5 turns showed the inductance of 2.7 nH and the quality factor more than 30 in the frequency region of 1 ㎓ and above. Also WLCSP-type integrated passive devices were fabricated using the high-performance spiral inductors. The fabricated low pass filter had a parallel-resonance circuit inside the spiral inductor to suppress 2nd harmonics and showed about 0.5 ㏈ insertion loss at 2.45 ㎓. And also the high/low-pass balun had the insertion loss less than 0.5 ㏈ and the phase difference of 182 degrees at 2.45 ㎓.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.484-487
• /
• 2015

This paper describes a dual-input battery charger with MPPT control using photovoltaic and piezoelectric energy. Each energy is harvested from photovoltaic cells and piezoelectric cells and is stored to each capacitor. The battery voltage is boosted by charger block and two energy sources are used as input to charge battery capacitor. A DC-DC boost converter is designed to boost the battery voltage, and inductor sharing technique is employed such that only one inductor is required. The time division ratio for piezoelectric cell and photovoltaic cell is set to 8:1. The proposed circuit is designed in a 0.35um CMOS process technology. The condition of battery capacitor is managed by battery management block and the battery voltage can be boosted up to 3V. The maximum efficiency of the designed entire system is 88.56%, and the chip area including pads is $1230um{\times}1330um$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.1
• /
• pp.100-108
• /
• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• Transactions on Electrical and Electronic Materials
• /
• v.12 no.6
• /
• pp.262-266
• /
• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.1
• /
• pp.60-68
• /
• 2016

This paper presents a 6~18 GHz 7-bit digital-controlled attenuator. The proposed attenuator is based on switched-T architecture, but no inductor is used for minimum chip size. The designed attenuator was fabricated using $0.18{\mu}m$ CMOS process, and characterized using on-wafer testing setup. The resolution(minimum attenuation step) and the maximum attenuation range of the attenuator were measured to be 0.22 dB and 28 dB, respectively. The measured RMS attenuation error and the RMS phase error for 6~18 GHz were less than 0.26 dB and $3.2^{\circ}$, respectively. The reference state insertion loss was less than 12.4 dB at 6~18 GHz. The measured input and output return losses were better than 9.4 dB over all frequencies and attenuation states. The chip size is $0.11mm^2$ excluding pads.