• 제목/요약/키워드: Chip assembly

검색결과 137건 처리시간 0.027초

반도체 조립공정의 화학물질 노출특성 및 작업환경관리 (Exposure Characteristics for Chemical Substances and Work Environmental Management in the Semiconductor Assembly Process)

  • 박승현;박해동;신인재
    • 한국산업보건학회지
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    • 제24권3호
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    • pp.272-280
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    • 2014
  • Objectives: The purpose of this study was to evaluate the characteristics of worker exposure to hazardous chemical substances and propose the direction of work environment management for protecting worker's health in the semiconductor assembly process. Methods: Four assembly lines at two semiconductor manufacturing companies were selected for this study. We investigated the types of chemicals that were used and generated during the assembly process, and evaluated the workers' exposure levels to hazardous chemicals such as benzene and formaldehyde and the current work environment management in the semiconductor assembly process. Results: Most of the chemicals used at the assembly process are complex mixtures with high molecular weight such as adhesives and epoxy molding compounds(EMCs). These complex mixtures are stable when they are used at room temperature. However workers can be exposed to volatile organic compounds(VOCs) such as benzene and formaldehyde when they are used at high temperature over $100^{\circ}C$. The concentration levels of benzene and formaldehyde in chip molding process were higher than other processes. The reason was that by-products were generated during the mold process due to thermal decomposition of EMC and machine cleaner at the process temperature($180^{\circ}C$). Conclusions: Most of the employees working at semiconductor assembly process are exposed directly or indirectly to various chemicals. Although the concentration levels are very lower than occupational exposure limits, workers can be exposed to carcinogens such as benzene and formaldehyde. Therefore, workers employed in the semiconductor assembly process should be informed of these exposure characteristics.

무작위 액중 상호 작용에 의한 단백질칩의 개발 (Development of Protein Chip by Random Fluidic Self-Assembly Interaction)

  • 최용성;권영수;박대희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.303-305
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    • 2003
  • In this paper, we have been proposed a new method of multichannel biosensor using random fluidic self-assembly. A metal particle and an array was fabricated. Biomaterials were immobilized on the metal particle. The array and the particles were mixed in a buffer solution, and were arranged by self-assembly. A quarter of total Ni dots were covered by the particles. The binding direction of the particles was controllable, and condition of particles was almost with Au surface on top. The particles were successfully arranged on the array. The biomaterial activities were detected by chemiluminescence.

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자기력에 의한 바이오칩의 개발 (Development of Biochip by Magnetic Force Interaction)

  • 최용성;박대희;권영수
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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    • pp.196-199
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    • 2003
  • In this paper, we have been described a new constructing method of multichannel biosensor using self-assembly by magnetic force interaction. A metal particle and an array was fabricated by photolithographic. Biomaterials were immobilized on the metal particle. The array and the particles were mixed in a buffer solution, and were arranged by magnetic force interaction and self-assembly. A quarter of total Ni dots were covered by the particles. The binding direction of the particles was controllable, and condition of particles was almost with Au surface on top. The particles were successfully arranged on the array. The biomaterial activities were detected by chemiluminescence.

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전기 및 유체 동시접속이 가능한 멀티칩 미소전기유체통합벤치의 설계, 제작 및 성능시험 (A Multi-chip Microelectrofluidic Bench for Modular Fluidic and Electrical Interconnections)

  • 장성환;석상도;조영호
    • 대한기계학회논문집A
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    • 제30권4호
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    • pp.373-378
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    • 2006
  • We present the design, fabrication, and characterization of a multi-chip microelectrofluidic bench, achieving both electrical and fluidic interconnections with a simple, low-loss and low-temperature electrofluidic interconnection method. We design 4-chip microelectrofluidic bench, having three electrical pads and two fluidic I/O ports. Each device chip, having three electrical interconnections and a pair of two fluidic I/O interconnections, can be assembled to the microelectofluidic bench with electrical and fluidic interconnections. In the fluidic and electrical characterization, we measure the average pressure drop of $13.6{\sim}125.4$ Pa/mm with the nonlinearity of 3.1 % for the flow-rates of $10{\sim}100{\mu}l/min$ in the fluidic line. The pressure drop per fluidic interconnection is measured as 0.19kPa. Experimentally, there are no significant differences in pressure drops between straight channels and elbow channels. The measured average electrical resistance is $0.26{\Omega}/mm$ in the electrical line. The electrical resistance per each electrical interconnection is measured as $0.64{\Omega}$. Mechanically, the maximum pressure, where the microelectrofluidic bench endures, reaches up to $115{\pm}11kPa$.

DNA Chip 제작을 위한 Microarrayer의 개발 (Development of Microarrayer for DNA Chips)

  • 김석열;정남수;이재성;김상봉
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2003년도 춘계학술대회
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    • pp.899-904
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    • 2003
  • Microarrayer makes DNA chip and microarray that contain hundreds to thousands of immobilized DNA probes on surface of a microscope slide. This paper shows the development results for a printing type of microarrayer. It realizes a typical, low-cost and efficient microarrayer for generating low density microarray. The microarrayer is developed by using a robot of three-axes perpendicular type. It is composed of a computer-controlled three-axes robot and a pen tip assembly. The key component of the arrayer is the print-head containing the tips to immobilize cDNA, genomic DNA or similar biological material on glass surface. The robot is designed to automatically collect probes from two 96-well plates with up to 32 tips at the same time. To prove the performance of the developed microarrayer, the general water types of inks such as black, blue and red. The inks are distributed at proper positions of 96 well plates and the three color inks are immobilized on the slide glass under the operation procedure. As the result of the test, it can be shown that it has sufficient performance for the production of low integrated DNA chip consisted of 96 spots within 1 $cm^2$ area.

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플립칩 패키지 구성 요소의 열-기계적 특성 평가 (Thermo-Mechanical Interaction of Flip Chip Package Constituents)

  • 박주혁;정재동
    • 한국정밀공학회지
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    • 제20권10호
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    • pp.183-190
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    • 2003
  • Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

칩마운터의 직진 테이프 피더 설계 및 평가 (Mechanical Design and Evaluation of Linear Tape Feeder for Chip Mounter)

  • 이수진;강성민;이창희;김용연
    • 한국정밀공학회지
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    • 제23권5호
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    • pp.155-161
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    • 2006
  • This paper introduces a new type of mechanical tape feeder for chip mounter. The mechanical feeder is composed of a pneumatic linear actuator and a linear feeding module with the application of a cam-slider. As semiconductor chips are getting smaller, PCB assembly makers require the feeder to position the chip with high accuracy. The linear feeding system improves the positioning accuracy of the chip by getting rid of the index error, which brings into existence on the sprocket rotating feeder. It also can make greatly reduce the dumping rate. The dumping error is caused by the impact occurred as the pawl to interrupt ratchet wheel rotation. The paper discusses its mechanism and mechanical performance. The positioning accuracy and the dynamic characteristic were measured for long time operation and analyzed. As a result, the feeder showed very good performance. However, the feeding system was dynamically unstable due to the cover film eliminator that is required to be modified

X선 영상의 에지 추출을 통한 플립칩 솔더범프의 접합 형상 오차 검출 (Detection of Flip-chip Bonding Error Through Edge Size Extraction of X-ray Image)

  • 송춘삼;조성만;김준현;김주현;김민영;김종형
    • 제어로봇시스템학회논문지
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    • 제15권9호
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    • pp.916-921
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    • 2009
  • The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

Characteristics of Lead Frame Chip Scale Package(LF-CSP)

  • Hong, Sung-Hak
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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    • pp.63-85
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    • 1999
  • $\cdot$New CSP using Lead Frame and solder ball techniques. $\cdot$EMC needs high filler content, low CTE and high flexural modulus. $\cdot$Solder Joint Reliability improved by anchor leads. .Uniform inner lead shape would be better at capacitance values. $\cdot$Low Assembly cost CSP.

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Copper Interconnection and Flip Chip Packaging Laboratory Activity for Microelectronics Manufacturing Engineers

  • Moon, Dae-Ho;Ha, Tae-Min;Kim, Boom-Soo;Han, Seung-Soo;Hong, Sang-Jeen
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.431-432
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    • 2012
  • In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

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