• 제목/요약/키워드: Chip Mounting Technology

검색결과 38건 처리시간 0.021초

Comparison of Driving Time between Stop-motion Method and Moving-motion Method

  • Kim, Soon-Ho;Kim, Chi-Su
    • 한국정보기술학회 영문논문지
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    • 제8권2호
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    • pp.139-145
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    • 2018
  • Improvement of the speed of the gantry among equipment that mounts a chip using SMT can improve productivity. In order to improve the performance of the gantry, there are studies such as a method of increasing the speed of adsorption, the speed of the gantry by reducing the weight, and a method of facilitating the use of the gantry. But all of these are ways of improving equipment. In this paper, we propose a method to improve the speed of gantry mounting microchip. The method is to shorten the driving time of the gantry. To do this, calculate the driving time using the existing method. And we calculate the travel time using the method presented in this paper. As a result, the time calculated by the proposed method is reduced by 14%.

다꾸찌방법을 사용한 여러변수들이 패키지균열에 미치는 신뢰도 평가 (Estimate of package crack reliabilities on the various parameters using taguchi's method)

  • 권용수;박상선;박재완;채영석;최성렬
    • 대한기계학회논문집A
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    • 제21권6호
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    • pp.951-960
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    • 1997
  • Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the maximum energy release rate criterion. It could be shown that the crack propagation from the lower edge of the ie pad is easily occurred at the maximum temperature during the soldering process, where the pressure acting on the crack surface is assumed by the saturated vapor pressure at maximum temperature. The package crack formation depends on various parameters such as chip size, relative thickness, material properties, the moisture content and soldering temperature etc. The quantitative measure of the effects of the parameters could be easily obtained by using the taguchi's method which requires only a few kinds of combinations with such parameters. From the results, it could be obtained that the more significant parameters to effect the package reliability are the orders of Young's modulus, die pad size, down set, chip thickness and maximum soldering temperature.

Development of Miniature Quad SAW Filter Bank based on PCB Substrate

  • Lee, Young-Jin;Kim, Chang-Il;Paik, Jong-Hoo
    • Transactions on Electrical and Electronic Materials
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    • 제9권1호
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    • pp.33-37
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    • 2008
  • This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

자동차 글라스 조립 자동화설비를 위한 FPGA기반 실러 도포검사 비전시스템 개발 (Development of an FPGA-based Sealer Coating Inspection Vision System for Automotive Glass Assembly Automation Equipment)

  • 김주영;박재률
    • 센서학회지
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    • 제32권5호
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    • pp.320-327
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    • 2023
  • In this study, an FPGA-based sealer inspection system was developed to inspect the sealer applied to install vehicle glass on a car body. The sealer is a liquid or paste-like material that promotes adhesion such as sealing and waterproofing for mounting and assembling vehicle parts to a car body. The system installed in the existing vehicle design parts line does not detect the sealer in the glass rotation section and takes a long time to process. This study developed a line laser camera sensor and an FPGA vision signal processing module to solve this problem. The line laser camera sensor was developed such that the resolution and speed of the camera for data acquisition could be modified according to the irradiation angle of the laser. Furthermore, it was developed considering the mountability of the entire system to prevent interference with the sealer ejection machine. In addition, a vision signal processing module was developed using the Zynq-7020 FPGA chip to improve the processing speed of the algorithm that converted the profile to the sealer shape image acquired from a 2D camera and calculated the width and height of the sealer using the converted profile. The performance of the developed sealer application inspection system was verified by establishing an experimental environment identical to that of an actual automobile production line. The experimental results confirmed the performance of the sealer application inspection at a level that satisfied the requirements of automotive field standards.

PCB에 장착된 SMD 의 부분영상을 이용한 리드의 최대 벗어난 양의 측정 (Measurement of maximum deviation of leads using partial image of SMD mounted on PCB)

  • 신동원;유준호
    • 제어로봇시스템학회논문지
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    • 제5권6호
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    • pp.698-704
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    • 1999
  • There are several types of defects of SMDs mounted on PCB, that is, missing components, misalignment, wrong parts and poor solder joints. This research study mainly focuses on measuring of deviation of SMD leads using the partial image of component, not using the full image. This processing based on the partial image has the advantage of the reduction in calculation time compared to the full image. Since position of lead is calculated with respect of the reduction in calculation time compared to the full image. Since position of lead is calculated with respect to pad, the accuracy of the system is not dependent on percise positioning stage. The grabbed image of gray scale is converted into binary format using a cutomatic threshold. After small fragments in the image is removed by a series of morphology operations such as opening and closing, the centroids of PCB pads and SMD leads is obtained together with labeling of blobs. Translational shift and rotationial angle of SMD are succedingly estimated using above information and chip data. The expression that can calculate the maximum deviation of leads with respect to PCB pads has been derived, and inferior mounting of SMD is judged by a given criterion. Some experiments have been executed to verify this measuring scheme.

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휴대기기용 DC-DC 부스트 컨버터 집적회로설계 (Design of a DC-DC Converter for Portable Device)

  • 이자경;송한정
    • 한국산업정보학회논문지
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    • 제22권2호
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    • pp.71-78
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    • 2017
  • 본 논문에서는 휴대기기용 DC-DC 부스트 컨버터를 설계하였다. 제안하는 DC-DC 부스트 컨버터는 1MHz의 스위칭 주파수로 구동되며, 인덕터, 출력 커패시터, MOS 트랜지스터 등으로 이루어지는 파워단 부분과 보호회로단, 컨트롤블럭단으로 구성하였다. CMOS magnachip $0.18{\mu}m$ 공정을 이용하여 SPICE 모의실험을 통하여 동작을 확인하였고, 칩을 제작하여 모의실험결과와 비교 분석하였다. 설계된 컨버터는 3.3 V 입력 전압 조건에서 출력전압 4.8 V 가 나타났고, 출력전류 95 mA 로 기존의 25~50 mA보다 큰 출력을 얻었다.

Critical Cleaning Requirements for Back End Wafer Bumping Processes

  • Bixenman, Mike
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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    • pp.57-64
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    • 2000
  • As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

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Critical Cleaning Requirements for Back End Wafer Bumping Processes

  • Bixenman, Mike
    • 마이크로전자및패키징학회지
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    • 제7권1호
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    • pp.51-59
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    • 2000
  • As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

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솔더접합부에 대한 기계적 스트레스 평가 (Evaluation of Mechanical Stress for Solder Joints)

  • 김정관
    • 마이크로전자및패키징학회지
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    • 제9권4호
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    • pp.61-68
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    • 2002
  • 지금까지 전자 디바이스의 솔더접합부에 대한 신뢰성 평가에 있어서는 열충격시험에 의한 평가가 주류를 이루었다. 그러나 최근 모바일 제품이 소형화/다기능화되고 고밀도실장에 대한 요구가 증가함에 따라 BGA/CSP와 같은 솔더볼을 사용하는 패키지가 표면실장의 주류를 이루게 되었으며, 솔더접합부에 대한 메커니컬 스트레스 수명이 요구되어지고 있다. BGA/CSP의 솔더접합부에 대한 신뢰성 평가는 하중을 가한 상태에서 데이지체인 패턴의 전기적 저항변화와 스트레인 게이지에 의한 스트레스-스트레인 커브에 의해 행해진다. 본 연구에서는 자체 개발한 PCB만능시험장치의 응용과 솔더접합부에 대한 메커니컬 스트레스의 동적거동을 평가한 소니의 실험자료를 소개하도록 한다.

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원칩 마이크로 컴퓨터(MCS-51)를 이용(移用)한 스피드 스프레이어의 원격조종(遠隔操縱) 변속장치(變速裝置) 개발(開發) (Development of Remote Control Transmission based on an One-chip Microcomputer in Speed Sprayer asture Plant Genetic Resources)

  • 장익주
    • Current Research on Agriculture and Life Sciences
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    • 제8권
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    • pp.107-113
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    • 1990
  • 본(本) 연구(硏究)는 고성능(高性能) 농약(農藥) 살포기인 스피드 스프레이어에 있어서 농약(農藥)살포 시(時) 인체(人體)에 해로운 농약(農藥)으로부터 오퍼레이터를 보호(保護)하기 위하여 무인(無人) 운전(運轉) 연구(硏究)의 일환(一環)으로 원칩 마이크로 컴퓨터를 이용(利用)하여 원격조종(遠隔操縱) 변속장치(變速裝置)를 개발(開發)할 목적(目的)으로 수행(遂行)한 연구(硏究)에서 얻어진 결과(結果)를 要約(요약)하면 다음과 같다. 1. 시작(試作)한 원칩 마이크로 컴퓨터를 이용(利用)한 원격조종(遠隔操縱) 변속장치(變速裝置)는 변속조작(變速操作) 100회(回) 중(中) 오동작(吳動作)이 전무(全無)하여 조작성(操作性)이 정확(正確)하였다. 2. 使用된 원칩 마이크로 컴퓨터의 프로그램은 기계어(機械語)로 작성(作成)되었으며, 변속조작(變速操作) 시간(時間)이 3초(初) 이내(以內)로 사람에 의한 변속조작(變速操作) 시간(時間)과 거의 같았다. 3. 본(本) 연구(硏究)에 사용(使用)한 원칩 마이크로 컴퓨터는 지금까지 자동화(自動化) 장치(裝置)에 많이 도입(導入) 사용(使用)하던 퍼스널 컴퓨터, 랩탑 컴퓨터, 원 보오도 컴퓨터 등과 비교하여 볼 때 극소형(極小型)으로 소비전력(消費電力)이 작으며 염가(廉價)이기 때문에 농업용(農業用)으로 적합(適合)하다고 사료(思料)된다. 4. 본(本) 연구(硏究)에 사용(使用)된 변속장치(變速裝置)는 승용(乘用) 농업기계(農業機械)와 같은 형식(形式)의 것이므로 농업용(農業用) 트렉터 및 포장기계(圃場機械)의 자동화(自動化) 기계(機械)에도 적용(適用)될 것으로 판단(判斷)된다. 5. 본(本) 실험장치(實驗裝置)는 직접(直接)레버조작(操作) 및 원격조종(遠隔操縱)이 동시(同時)에 이루어지도록 제작(製作)하였기 때문에 구조적(構造的)으로 복잡(複雜)하나 직접(直接)레버 조작부(操作部)를 제거(除去)하고 원격조종부(遠隔操縱部)만 스피드 스프레이어에 장착(裝着)하면 더욱더 소형화(小型化) 되고 중량(重量)도 더 가벼워져 사용(使用)하기에 편리(便利)한 장치(裝置)가 될 것으로 사료(思料)된다.

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