• 한국멀티미디어학회논문지
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• 제18권2호
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

• 한국정밀공학회지
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• 제31권5호
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• pp.395-401
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• 2014

Development of five axis tool grinding machine and CAD/CAM systems increase tool design flexibility. In this research, investigated are cutting characteristics of ball-end mill with different helix angle. Special WC ball-end mills with $0^{\circ}$, $10^{\circ}$, $20^{\circ}$, $30^{\circ}$ helix angles are designed and used in various cutting tests. Machining performance according to helix angle variation is evaluated from cutting forces, surface roughness, tool wear, produced chip shape, and vibration characteristics. The ball-end mill with $10^{\circ}$ helix angle shows the best cutting performance due to appropriate chip load distribution and smooth chip flow. This research can be used for cutting edge geometry optimization and novel design of ball-end mill.

• 한국화재소방학회논문지
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• 제10권2호
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 춘계학술대회
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• pp.888-889
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• 2015

본 논문에서는 입베디드세스템에 기초를 둔 시스템온칩을 구성하는 방법을 제안하였다. 제안한 방법은 이전의 방법에 비해 좀 더 콤팩트하고 효과적이다. 이 방법은 높은 수행시뮬레이션을 요구하고 하드웨어/소프트웨어 통합설계 툴을 사용하여 구현을 위한 실행 가능한 규격화된 적절함을 요구한다. 시스템 인터페이스 처럼 이미 존재하고 있는 부품의 재사용은 지원되지만, 작업 이후는 단지 하드웨어/소프트웨어 통합설계 툴의 프로그램에 의해 수행되어진다. 실제 설계 흐름은 모든 프로세스를 통하여 요구되는 구현으로부터 모든 설계 단계 사이의 궤환을 허용하게끔 설명되어진다. 향후 좀 더 진보된 임베디드시스템에 기초를 둔 시스템온칩을 구성하는 방법이 요구된다.

• International Journal of Stem Cells
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• 제17권1호
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• pp.30-37
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• 2024

The lung is a complex organ comprising a branched airway that connects the large airway and millions of terminal gas-exchange units. Traditional pulmonary biomedical research by using cell line model system have limitations such as lack of cellular heterogeneity, animal models also have limitations including ethical concern, race-to-race variations, and physiological differences found in vivo. Organoids and on-a-chip models offer viable solutions for these issues. Organoids are three-dimensional, self-organized construct composed of numerous cells derived from stem cells cultured with growth factors required for the maintenance of stem cells. On-a-chip models are biomimetic microsystems which are able to customize to use microfluidic systems to simulate blood flow in blood channels or vacuum to simulate human breathing. This review summarizes the key components and previous biomedical studies conducted on lung organoids and lung-on-a-chip models, and introduces potential future applications. Considering the importance and benefits of these model systems, we believe that the system will offer better platform to biomedical researchers on pulmonary diseases, such as emerging viral infection, progressive fibrotic pulmonary diseases, or primary or metastatic lung cancer.

• 대한화장품학회지
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• 제30권1호
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• pp.59-62
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• 2004

본 연구는 다양한 종류의 에멀젼에 전단응력을 가하며 그때 일어나는 에멀젼의 상 변이를 전기, 유변학적 특징을 통해 실시간으로 측정해보는 것이다. 전기 전도도의 변화는 자체 제작한 JELL $I^{TM}$ (Joint Electro-rheometer for Liquid-Liquid Inversion) 칩을 이용하였으며, 동시에 유변물성측정장치(rheometer)를 이용하여 유변물성의 변화를 측정하였다. JELL $I^{TM}$ 과 인조 피부를 유변물성측정장치 사이에 장착하고 그 사이에 다양한 종류의 에멀젼을 얇게 발라준 후, 일정한 전단응력을 주며 시간에 따른 저항과 전도값의 변화를 측정하였다. O/W 제형의 경우 시간에 따라 저항값이 커지는 경향을 보였으며 저항값은 내부 상이 많을 수록 더 급격한 변화를 나타냈다. 이때의 점도 변화를 보면, 저항값의 변화가 클수록 점도의 변화도 큼을 볼 수 있었다. 이것은 내부 상의 파괴로 인해 외부의 힘에 저항하는 힘이 약해졌기 때문이라고 예상된다. 이런 결과를 이용하여 전단응력에 의한 에멀젼 상 변이 특성과 정도를 실시간, 정량적 비교할 수 있었다., 정량적 비교할 수 있었다.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.61-71
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• 2007

프로세서 성능향상에 일반적으로 이용되어 오던 명령어 수준의 병렬성은 이제 그 한계를 드러내고 있다. 명령어 수준의 병렬성을 이용하는데 장애가 되는 요인 중에 하나는 분기문에 의한 제어 흐름의 변화이다. 단일 칩 멀티프로세서는 쓰레드 수준의 병렬성을 이용하는 프로세서이다. 그러나 다중 쓰레드를 고려하지 않고 작성된 프로그램을 수행하는 경우에는 단일 칩 멀티프로세서의 성능을 최대한 사용할 수 없는 단점이 있다. 이와 같은 두 가지 성능 저하 요인을 극복하기 위해 본 논문에서는 다중 경로 수행 기법을 단일 칩 멀티프로세서에 적용한 분기 동시 수행 기법을 제안한다. 제안된 방법에서는 유휴 중인 프로세서를 이용하여 조건 분기의 두 흐름을 모두 수행하게 한다. 이를 통하여 분기문에 의한 제어 흐름이 끊기는 것을 막고 유휴 시간을 줄여서 프로세서의 효율을 높일 수 있다. 시뮬레이션을 통하여 본 논문에서 제시한 분기 동시 수행의 효과를 분석한 결과 분기 동시 수행으로 약 20%의 유휴 시간이 감소하였고, 분기 예측 성공률은 최대 10% 향상 되었다. 전체적으로 일반적인 단일 칩 멀티프로세서에 비해 최대 39%의 성능 향상을 이루었고, 슈퍼스칼라 프로세서에 비해 최대 27%의 성능 향상을 이루었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• 한국가시화정보학회지
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• 제1권2호
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• pp.47-51
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• 2003

Microfluidic chips such as lab-on-a-chip (LOC) include micro-channels for sample delivery, mixing, reaction, and separation. Pressure driven flow or electro-osmotic flow (EOF) has been usually employed to deliver bio-samples. Having some advantages of easy control, the flow characteristics of EOF in microchannels should be fully understood to effectively control the electro-osmotic pump for bio-sam-pie delivery. In this study, a micro PIV system with an epifluorescence inverted microscope and a cooled CCD was used to measure velocity fields of EOF in a glass microchannel and a PDMS microchannel. The EOF velocity fields were changed with respect to electric charge of seeding particles and microchannel materials used. The EOF has nearly uniform velocity distribution inside the microchannel when pressure gradient effect is negligible. The mean streamwise velocity is nearly proportional to the applied electric field. Glass microchannels give better repeatability in PIV results, compared with PDMS microchannels which are easy to fabricate and more suitable for PIV experiments.