• Journal of Korea Multimedia Society
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• v.18 no.2
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.5
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• pp.395-401
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• 2014

Development of five axis tool grinding machine and CAD/CAM systems increase tool design flexibility. In this research, investigated are cutting characteristics of ball-end mill with different helix angle. Special WC ball-end mills with $0^{\circ}$, $10^{\circ}$, $20^{\circ}$, $30^{\circ}$ helix angles are designed and used in various cutting tests. Machining performance according to helix angle variation is evaluated from cutting forces, surface roughness, tool wear, produced chip shape, and vibration characteristics. The ball-end mill with $10^{\circ}$ helix angle shows the best cutting performance due to appropriate chip load distribution and smooth chip flow. This research can be used for cutting edge geometry optimization and novel design of ball-end mill.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.888-889
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• 2015

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Journal of the Society of Cosmetic Scientists of Korea
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• v.30 no.1
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• pp.59-62
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• 2004

To know what happens to the internal structure of emulsions under high shear flow is very important for cosmetic product development because it is highly relevant to the physical degradation of emulsions during the application upon the skin. Here, in order to investigate the response of emulsions against the external shear forces, we designed a new device, .JELLI$^{TM}$ (Joint Electro-rheometer for Liquid-Liquid Inversion) chip, for the measurement of electrical and rheological properties of emulsions under shear flow. By using this device, we examined the real-time changes in conductivities of oil-in-water (O/W) and water-in-oil (W/O) emulsions on the artificial skin during large deformation under shear flow. In this study, O/W and W/O emulsions having various volumes were prepared. After emulsions were homogeneously applied on the artificial skin, the electrical resistance and viscosity changes were monitored under steady shear flow. In case of O/W emulsions, the resistance increased as a function of time. The resistance showed more dramatic increase as the increase of the internal oil phase. It was also found that the viscosity change was proportional to the resistance variation. This phenomenon might be caused by decreased resisting forces against the shear flow because of the breakdown of the internal phase.the internal phase.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• Journal of the Korean Society of Visualization
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• v.1 no.2
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• pp.47-51
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• 2003

Microfluidic chips such as lab-on-a-chip (LOC) include micro-channels for sample delivery, mixing, reaction, and separation. Pressure driven flow or electro-osmotic flow (EOF) has been usually employed to deliver bio-samples. Having some advantages of easy control, the flow characteristics of EOF in microchannels should be fully understood to effectively control the electro-osmotic pump for bio-sam-pie delivery. In this study, a micro PIV system with an epifluorescence inverted microscope and a cooled CCD was used to measure velocity fields of EOF in a glass microchannel and a PDMS microchannel. The EOF velocity fields were changed with respect to electric charge of seeding particles and microchannel materials used. The EOF has nearly uniform velocity distribution inside the microchannel when pressure gradient effect is negligible. The mean streamwise velocity is nearly proportional to the applied electric field. Glass microchannels give better repeatability in PIV results, compared with PDMS microchannels which are easy to fabricate and more suitable for PIV experiments.

• Proceedings of the KSME Conference
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• 2002.08a
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• pp.487-490
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• 2002

The real chip and similarity model were used to investigate the thermal behavior and velocity distribution of air from the heat source with the location and the amount of heat experimentally and numerically, and compared. The heat generated in the block is not cooled by convection and show the high temperature by the stagnation of heat flow. After maintaining the high temperature of block by the natural convection, the sudden drop of temperature with the air flow was shown in the channel but the decreasing rate was small with the time. The inward block was effected by infinitesimal air flow generated between block and channel and outward block was effected by the entry condition.