• ETRI Journal
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• v.40 no.6
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1993.10a
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• pp.22-27
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• 1993

The finite element method is applied to analyze the mechanism of metal cutting. This paper introduces some effects, such constitutive deformation laws of workpiece material, friction of tool-chip contact interfaces, tool rake angles and also simulate the cutting process, chip formation and geometry, tool-chip contact, reaction force of tool, cutting temperature. Under the usual [lane strain assumption, quasi-static analysis were performed with variation of tool-chip interface friction coefficients and rake angles. In this analysis, various cutting speeds and depth of cut are adopted. Some cutting parameters are affected to cutting force, plastic deformation of chip, shear plane angle, chip thickness and tool-chip contact length and reaction forces on tool. Cutting temperature and Thermal behavior. Several aspects of the metal cutting process predicted by the finite element analysis provide information about tool shape design and optimal cutting conditions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.641-648
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• 2002

The study on the chip waveform design to minimize multiple-access interference (MAI) and its performance evaluation are very important since chip waveform decides the signal quality and system capacity of the direct-sequence CDMA wireless communication system. This paper suggests the analytical chip waveform to minimize the MAI. The BER and throughput performances achieved by the proposed analytical optimum chip waveform are compared with those of the conventional chip waveforms in the Nakagami-m distribution frequency selective channel when the differential phase shift keying (DPSK) is employed in DS-CDMA system. From the numerical results, capacity and throughput are improved about 2 times and 1.4 times respectively when it is compared with the Kaiser chip waveform that is considered as one of the best in the conventional ones.

• Journal of the Korean Society for Precision Engineering
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• v.10 no.4
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• pp.206-215
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• 1993

The finite element method is applied to analyze the mechanism of metal cutting, especially micro metal cutting. This paper introduces some effects, such as constitutive deformation laws of workpiece material, friction of tool-chip contact interfaces, tool rake angle and also simulate the cutting process, chip formation and geometry, tool-chip contact, reaction force of tool. Under the usual plane strain assumption, quasi-static analysis were performed with variation of tool-chip interface friction coefficients and tool rake angles. In this analysis, cutting speed, cutting depth set to 8m/sec, 0.02mm, respectively. Some cutting parameters are affected to cutting force, plastic deformation of chip, shear plane angle, chip thickness and tool-chip contact length and reaction forces on tool. Several aspects of the metal cutting process predicted by the finite element analysis provide information about tool shape design and optimal cutting conditions.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.173-176
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• 2000

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1475-1482
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• 2009

In this paper, a computer simulation is developed for isotachophoretic protein separation in a serpentine micro channel for optimal lab on a chip design using 2D Finite Element Method. This 2D ITP model is composed of 5 components such as hydrochloric acid as Leader, caproic acid as terminator, acetic acid and benzoic acid as two proteins, and histindine as background electrolyte. The computer model is based on mass conservation equation for 5 components, charge conservation equation for electric potential, and electro neutrality condition for pH calculation. For the validation of the 2D spatial ITP model, the results are compared with the Simul5 developed by Bohuslav Gas Group. The simulation results are in a good agreement in a ID planar channel. This proves the precision of our model. The 2Dproteinseparation is conducted in a 2D curved channel for Lab on a chip design and dispersions of proteins are revealed during the electrophoretic process in a curved shape.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Journal of Korea Multimedia Society
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• v.4 no.1
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• pp.82-90
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• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.3
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• pp.301-307
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• 2002

A multilayer ceramic chip antenna with helical structure is analyzed to enhance the narrow bandwidth of conventional ceramic chip antennas. The simulations are performed by HFSS to verify the effects of structural parameters on impedance bandwidth. The multilayer ceramic chip antennas consist of a rectangular-parallelepiped ceramic body$({\varepsilon}_r=7.8,\; tan\; {\delta}=0.0043)$ and helical conductor patterns are embedded in the ceramic body using LTCC-MLC technology. 3D structure design of the multilayer ceramic chip antenna suitable for IMT-2000 (1,920~2,170 MHz) handset has been implemented, and experimental results are presented and discussed.