• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1553-1571
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• 1993

A significant amount of research has focused on the development of highly parallel architectures to obtain far more computational power than conventional computer systems. These architectures usually comprise of a large number of processors communicating through an interconnection network. The VLSI (Very Large Scale Integration) and WSI (Wafer Scale Integration) cellular arrays form one important class of those parallel architectures, and consist of a large number of simple processing cells, all on a single chip or wafer, each interconnected only to its neighbors. This paper studies three fundamental issues in these arrays : fault-tolerant reconfiguration. functional reconfiguration, and their integration. The paper examines conventional techniques, and gives an in-depth discussion about fault-tolerant reconfiguration and functional reconfiguration, presenting testing control strategy, configuration control strategy, steps required f4r each reconfiguration, and other relevant topics. The issue of integrating fault tolerant reconfiguration and functional reconfiguration has been addressed only recently. To tackle that problem, the paper identifies the relation between fault tolerant reconfiguration and functional reconfiguration, and discusses appropriate testing and configuration control strategy for integrated reconfiguration on VLSI and WSI cellular arrays.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.12
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• pp.1380-1387
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• 2012

The transmit/receive(T/R) module is a key component in the active phased array system. The brick-type T/R module has been widely used and the miniaturization has been an important factor to get the flexibility of the system configuration. For the miniaturization, multi-function chips(MFC) having a common leg configuration are suitable to reduce the number of required MMICs and a high isolation between transmit and receive paths is necessary for the high gain T/R modules. In this work, we propose a bias timing scheme for the compact T/R module and show the optimum timing based on measurements, in order to improve the feed-back path loop problem and the consequent isolation problem of the common leg configuration. We have implemented high power(7 W/channel) and high T/R gain(35 dB transmit and 30 dB receive gains) within the half size($140{\times}80{\times}16mm^3$) of the conventional T/R modules.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.415-418
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• 2007

This paper presents the design and analysis of LNA-Mixer for 2.45GHz RFID reader. The LNA is implemented by PCSNIM method for low power consumption. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique, and the resonating technique for the tail capacitance. The connection between the two designed circuits is made by active balun. This LNA-Mixer has about 35dB for -40dBm input RF power, LO power is 0dBm and RF frequency is 2.45 GHz and IIP3 is -4dBm. The layout of LNA-Mixer for one-chip design in a $0.18-{\mu}m$ TSMC process has 2.6mm ${\times}$ 1.3mm size.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1161-1164
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• 1992

In this paper demonstrates the possibiity of utilising clamped mode - series resonant converter technology in the high frequency link inverter configuration. Main circuit of the proposed inverter is analyzed through circuit analys and waveform simulation. In control circuit PLL circuit and 8 bit single chip microcontroller is adopted, therefore flexibility and accuracy of control circuit is increased.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.11
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• pp.1018-1026
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• 2012

This paper presents a developing method of smart fingerprint recognition system. First, we design a hardware configuration circuit using a 32bit Risc CPU, a fingerprint sensor, a LCD, and a WiFi communication chip to realize the smart fingerprint recognition systems. It is necessary to develop a JNI (Java Native Interface) library and a device drive program of fingerprint sense to develop application program of fingerprint recognition system with Android platform. Thus second, we develop a device drive and a JNI program. And we also develop an application program of fingerprint recognition systems using developed JNI library. Finally test results are presented to illustrate the performance of the developed smart fingerprint recognition system.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.165-168
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• 2001

This Paper presents the design method and performance characteristics of a dual band balun. The design method for dual balun is based on the lumped element eqiuvalent circuit of quater-wave transformaer. By employing the proposed configuration and the derived formulas, dual band balun are designed and simulated and manufactured. The proposed design method and equivalent circuit can make it easy to adapt to designing of ceramic multi-layer chip type dual band balun. The dual band will find applications in wireless communication circuits.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1995.10a
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• pp.60-63
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• 1995

The behavior of the work materials in the chip-tool interface in extremely high strain rates and temperatures is more that of viscous liquids than that of normal solid metals. In these circumstances the principles of fluid mechanics can be invoked to describe the metal flow in the neighborhood of the cutting edge. In the present paper an Eulerian finite element model is presented that simulates metal flow in the vicinity of the cutting edge when machining a low carbon steel with carbide cutting tool. The work material is assumed to obey visco-plastic (Bingham solid) constitutive law and Von Mises criterion. Heat generation is included in the model, assuming adiabatic conditions within each element. the mechanical and thermal properties of the work material are accepted to vary with the temperature. The model is based on the virtual work-stream function formulation, emphasis is given on analyzing the formation of the stagnant metal zone ahead of the cutting edge. The model predicts flow field characteristics such as material velocity effective stress and strain-rate distributions as well as built-up layer configuration

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.222-224
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• 2006

To improve the drawback of LCMPPT(Limit Cycle Maximum Power Point Tracking) controller of the existing two power conversion stages, an advanced MPPT scheme of single power conversion stage is proposed in this paper. This topology is faster on the control speed by means of current control method and the system configuration is simpler. The Authors produce a battery charger by using a cost effective one-chip processor (PIC16F877A) and evaluate another application on the basis of simulation. As a result, the proposed new LCMPPT algorithm is confirmed to be stable and useful.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.754-758
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• 1996

This paper presents a new approach to the design of self-tuning adaptive control system that is robust to the changing dynamic configuration as well as to the load variation factors using Digital signal processors for robot manipulators. TMS320C50 is used in implementing real-time adaptive control algorithms to provide advanced performance for robot manipulator, In this paper, an adaptive control scheme is proposed in order to design the pole-placement self-tuning controller which can reject the offset due to any load disturbance without a detailed description of robot dynamics. Parameters of discrete-time difference model are estimated by the recursive least-square identification algorithm, and controller parameters we determined by the pole-placement method. Performance of self-tuning adaptive controller is illusrated by the simulation and experiment for a SCARA robot.