• Journal of the Korean Society for Heat Treatment
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• v.31 no.4
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• pp.187-193
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• 2018

In this study, the electrical conductivity, transmittance and gas barrier properties of diamond-like carbon (DLC) thin films were studied. DLC is an insulator, and has transmittance and oxygen gas barrier properties varying depending on the thickness of the thin film. Recently, many researchers have been trying to apply DLC properties to specific industrial conditions. The DLC thin films were deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) process. The doping gas was used for the DLC film to have electrical conductivity, and the optimum conditions of transmittance and gas barrier properties were established by adjusting the gas ratio and DLC thickness. In order to improve the electrical conductivity of the DLC thin film, $N_2$ doping gas was used for $CH_4$ or $C_2H_2$ gas. Then, a heat treatment process was performed for 30 minutes in a box furnace set at $200^{\circ}C$. The lowest sheet resistance value of the DLC film was found to be $18.11k{\Omega}/cm^2$. On the other hand, the maximum transmittance of the DLC film deposited on the PET substrate was 98.8%, and the minimum oxygen transmission rate (OTR) of the DLC film of $C_2H_2$ gas was 0.83.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.642-642
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• 2013

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as high electron mobility, high thermal conductivity and optical transparency. Especially, chemical vapor deposition (CVD) grown graphene has been used as a promising material for high quality and large-scale graphene film. Unfortunately, although CVD-grown graphene has strong advantages, application of the CVD-grown graphene is limited due to ineffective transfer process that delivers the graphene onto a desired substrate by using polymer support layer such as PMMA(polymethyl methacrylate). The transferred CVD-grown graphene has serious drawback due to remaining polymeric residues generated during transfer process, which induces the poor physical and electrical characteristics by a p-doping effect and impurity scattering. To solve such issue incurred during polymer transfer process of CVD-grown graphene, various approaches including thermal annealing, chemical cleaning, mechanical cleaning have been tried but were not successful in getting rid of polymeric residues. On the other hand, lithographical patterning of graphene is an essential step in any form of microelectronic processing and most of conventional lithographic techniques employ photoresist for the definition of graphene patterns on substrates. But, application of photoresist is undesirable because of the presence of residual polymers that contaminate the graphene surface consistent with the effects generated during transfer process. Therefore, in order to fully utilize the excellent properties of CVD-grown graphene, new approach of transfer and patterning techniques which can avoid polymeric residue problem needs to be developed. In this work, we carried out transfer and patterning process simultaneously with no polymeric residue by using a metal etch mask. The patterned thin gold layer was deposited on CVD-grown graphene instead of photoresists in order to make much cleaner and smoother surface and then transferred onto a desired substrate with PMMA, which does not directly contact with graphene surface. We compare the surface properties and patterning morphology of graphene by scanning electron microscopy (SEM), atomic force microscopy(AFM) and Raman spectroscopy. Comparison with the effect of residual polymer and metal on performance of graphene FET will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.171-176
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• 1999

${\gamma}-Fe_2O_3$ thin films on $Al_2O_3$ substrate were prepared by the oxidation of $Fe_3O_4$ thin films processed by PECVD(Plasma-Enhanced Chemical Vapor Deposition) technique. The phase transformation of ${\gamma}-Fe_2O_3$ thin films was mainly controlled by the substrate temperature and oxidation process of $Fe_3O_4$ phase. $Fe_3O_4$ phase was obtained at the deposition temperature of $200{\sim}300^{\circ}C$. $Fe_3O_4$ phase could be transformed into ${\gamma}-Fe_2O_3$ phase under controlled oxidation at $280{\sim}300^{\circ}C$. $Fe_3O_4$ and ${\gamma}-Fe_2O_3$ obtained by oxidation of $Fe_3O_4$ phase had the same spinel structure and were coexisted. The oxidized ${\gamma}-Fe_2O_3$ thin film on $Al_2O_3$ substrate showed a porous island structure.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.150.1-150.1
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• 2014

Showerhead is used as a main part in the semiconductor equipment. The face plate flatness should remain constant and the cleaning performance must be gained to keep the uniformity level of etching or deposition in chemical vapor deposition process. High operating temperature or long period of thermal loading could lead the showerhead to be deformed thermally. In some case, the thermal deformation appears very sensitive to showerhead performance. This paper describes the methods for robust design using computational fluid dynamics. To reveal the influence of the post distribution on flow pattern in the showerhead cavity, numerical simulation was performed for several post distributions. The flow structure appears similar to an impinging flow near a centered baffle in showerhead cavity. We took the structure as an index to estimate diffusion path. A robust design to reduce the thermal deformation of showerhead can be achieved using post number increase without ill effect on flow. To prevent the showerhead deformation by heat loading, its face plate thickness was determined additionally using numerical simulation. The face plate has thousands of impinging holes. The design key is to keep pressure drop distribution on the showerhead face plate with the holes. This study reads the methodology to apply to a showerhead hole design. A Hagen-Poiseuille equation gives the pressure drop in a fluid flowing through such hole. The assumptions of the equation are the fluid is viscous-incompressible and the flow is laminar fully developed in a through hole. An equation can be expressed with radius R and length L related to the volume flow rate Q from the Hagen-Poiseuille equation, $Q={\pi}R4{\Delta}p/8{\mu}L$, where ${\mu}$ is the viscosity and ${\Delta}p$ is the pressure drop. In present case, each hole has steps at both the inlet and the outlet, and the fluid appears compressible. So we simplify the equation as $Q=C(R,L){\Delta}p$. A series of performance curves for a through hole with geometric parameters were obtained using two-dimensional numerical simulation. We obtained a relation between the hole diameter and hole length from the test cases to determine hole diameter at fixed hole length. A numerical simulation has been performed as a tool for enhancing showerhead robust design from flow structure. Geometric parameters for the design were post distribution and face plate thickness. The reinforced showerhead has been installed and its effective deposition profile is being shown in factory.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.162-162
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• 2010

InSb has received great attentions as a promising candidate for the active layer of infrared photodetectors due to the well matched band gap for the detection of $3{\sim}5\;{\mu}m$ infrared (IR) wavelength and high electron mobility (106 cm2/Vs at 77 K). In the fabrication of InSb photodetectors, passivation step to suppress dark currents is the key process and intensive studies were conducted to deposit the high quality passivation layers on InSb. Silicon dioxide (SiO2), silicon nitride (Si3N4) and anodic oxide have been investigated as passivation layers and SiO2 is generally used in recent InSb detector fabrication technology due to its better interface properties than other candidates. However, even in SiO2, indium oxide and antimony oxide formation at SiO2/InSb interface has been a critical problem and these oxides prevent the further improvement of interface properties. Also, the mechanisms for the formation of interface phases are still not fully understood. In this study, we report the quantitative analysis of indium and antimony oxide formation at SiO2/InSb interface during plasma enhanced chemical vapor deposition at various growth temperatures and subsequent heat treatments. 30 nm-thick SiO2 layers were deposited on InSb at 120, 160, 200, 240 and $300^{\circ}C$, and analyzed by X-ray photoelectron spectroscopy (XPS). With increasing deposition temperature, contents of indium and antimony oxides were also increased due to the enhanced diffusion. In addition, the sample deposited at $120^{\circ}C$ was annealed at $300^{\circ}C$ for 10 and 30 min and the contents of interfacial oxides were analyzed. Compared to as-grown samples, annealed sample showed lower contents of antimony oxide. This result implies that reduction process of antimony oxide to elemental antimony occurred at the interface more actively than as-grown samples.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2075-2082
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• 2006

This paper presents modeling and optimization techniques for hish efficiency solar cell process on single-crystalline float zone (FZ) wafers. Among a sequence of multiple steps of fabrication, the followings are the most sensitive steps for the contact formation: 1) Emitter formation by diffusion; 2) Anti-reflection-coating (ARC) with silicon nitride using plasma-enhanced chemical vapor deposition (PECVD); 3) Screen-printing for front and back metalization; and 4) Contact formation by firing. In order to increase the performance of solar cells in terms of efficiency, the contact formation process is modeled and optimized using neural networks and genetic algorithms, respectively. This paper utilizes the design of experiments (DOE) in contact formation to reduce process time and fabrication costs. The experiments were designed by using central composite design which consists of 24 factorial design augmented by 8 axial points with three center points. After contact formation process, the efficiency of the fabricated solar cell is modeled using neural networks. Established efficiency model is then used for the analysis of the process characteristics and process optimization for more efficient solar cell fabrication.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.651-654
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• 2010

This paper describes the thermal and mechanical properties of doped thin film 3C-SiC and porous 3C-SiC. In this work, the in-situ doped thin film 3C-SiC was deposited by using atmospheric pressure chemical vapor deposition (APCVD) method at $120^{\circ}C$ using single-precursor hexamethyildisilane: $Si_2(CH_3)_6$ (HMDS) as Si and C precursors. 0~40 sccm $N_2$ gas was used as doping source. After growing of doped thin film 3C-SiC, porous structure was achieved by anodization process with 380 nm UV-LED. Anodization time and current density were fixed at 60 sec and 7.1 mA/$cm^2$, respectively. The thermal and mechanical properties of the $N_2$ doped porous 3C-SiC was measured by temperature coefficient of resistance (TCR) and nano-indentation, respectively. In the case of 0 sccm, the variations of TCR of thin film and porous 3C-SiC are similar, but TCR conversely changed with increase of $N_2$ flow rate. Maximum young's modulus and hardness of porous 3C-SiC films were measured to be 276 GPa and 32 Gpa at 0 sccm $N_2$, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.375.2-375.2
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• 2016

그래핀(Graphene)은 원자 한 층 두께의 얇은 특성에 기인하여 우수한 투과도(~97.3%)를 나타내며, 높은 전자 이동도($200,000cm^2V^{-1}s^{-1}$)로 인하여 전기 전도도가 우수한 2차원 전자소재이다. 또한 유연하고 우수한 기계적 물성을 가지고 있어 실제로 다양한 소자에서 활용되고 있다. 그래핀을 이용하여 다양한 소자로 응용하기 위한 과정 중 하나인 포토리소그래피 공정(Photolithography process)은 원하는 패턴을 만들기 위해 제작하고자 하는 기판 위에 포토레지스트(Photoresist)를 코팅하는 과정을 거치게 된다. 하지만 이러한 과정은 소자 제작에 있어서 포토레지스트 잔여물을 남기게 된다. 그래핀 위에 남은 포토레지스트 잔여물은 그래핀의 우수한 전기적 특성을 저하시켜 소자특성에 불이익을 주게 된다. 본 연구에서는 수소 플라즈마를 이용하여 그래핀 위에 남은 중합체(Polymer) 잔여물을 제거한다. 사용한 그래핀은 화학 기상 증착법(Chemical vapor deposition)을 이용하여 성장시켰으며, PMMA(Poly(methyl methacrylate))를 이용하여 이산화규소(silicon dioxide) 기판에 전사하였다. 그래핀의 손상 없이 중합체 잔여물을 제거하기 위해 플라즈마 처리시간을 15초부터 1분까지 늘려가며 연구를 진행하였으며, 플라즈마 처리 시간에 따른 중합체 잔여물의 제거 정도와 그래핀의 보존 여부를 확인하기 위해 라만 분광법(Raman spectroscopy)과 원자간력현미경(Atomic force microscopy)을 사용하였다. 본 연구 결과를 통해 간단한 플라즈마 처리로 보다 나은 특성의 그래핀 소자를 얻게 됨으로써, 향상된 특성을 가진 그래핀 소자로 산업적 응용 가능성을 높일 수 있을 것이라 생각된다.