• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.120-120
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• 2011

Graphene is a carbon based material and it has great potential of being utilized in various fields such as electronics, optics, and mechanics. In order to develop graphene-based logic systems, graphene field-effect transistor (GFET) has been extensively explored. GFET requires supporting devices, such as volatile memory, to function in an embedded logic system. As far as we understand, graphene has not been studied for volatile memory application, although several graphene non-volatile memories (GNVMs) have been reported. However, we think that these GNVM are unable to serve the logic system properly due to the very slow program/read speed. In this study, a GVM based on the GFET structure and using an engineered graphene channel is proposed. By manipulating the deposition condition, charge traps are introduced to graphene channel, which store charges temporarily, so as to enable volatile data storage for GFET. The proposed GVM shows satisfying performance in fast program/erase (P/E) and read speed. Moreover, this GVM has good compatibility with GFET in device fabrication process. This GVM can be designed to be dynamic random access memory (DRAM) in serving the logic systems application. We demonstrated GVM with the structure of FET. By manipulating the graphene synthesis process, we could engineer the charge trap density of graphene layer. In the range that our measurement system can support, we achieved a high performance of GVM in refresh (>10 ${\mu}s$) and retention time (~100 s). Because of high speed, when compared with other graphene based memory devices, GVM proposed in this study can be a strong contender for future electrical system applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.944-948
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• 2011

In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/$SiO_2$ interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.

• Proceedings of the ESK Conference
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• 1992.10a
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• pp.63-67
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• 1992

인간이 역사를 이루며 살아오면서 피복은 인간의 생활 수단으로서 빠뜨릴 수 없는 존재가 되었다. 사외 생활을 하면서 인간은 자신을 보호하고 남에게 자신의 이미지를 전달하고 자신의 욕구를 표출하면서 만족시키는데 있어 의복은 가장 중요한 역활을 하고 있고 인간 역시 그러한 것들을 의복에 의존하고 있는 것이다. 그러나 정상인을 위한 의복만 취급되어지는 시장에서 신체장애자들은 정상인보다도 더 세심하게 기능들이 고려된 의복이 필요함에도 불구하고 의복의 기능들을 생각하면서 의복을 선택할 수가 없다. 이러한 사앙들이 대두되면서 현대에 들어 신체 장애자 의복에 있어서 불편함을 없애고 보다 적합한 의복을 만들기 위한 연구가 진행되었다. 신체 장애자의 의복 연구는 Ward가 이 부분에 관심을 표명한 이후 임상 의사들에 의해 연구가 이루어지기 시작했다. 우리나라에서도 1976년 심성식의 한국 신체 장애자의 의복에 관한 연구를 기점으로 이 분야의 관심도가 높아지고 있으나 아직까지는 전반적으로 부족한 실정이다. 특히 위생적인 분야에서는 자료가 매우 부족하다. 이에 본 연구에서는 휠체어를 사용하는 하지 마비자의 체표 면을 떠서 기성복 패턴과 비교를 통해 보다 편안한 바지 패턴을 제시하고, 여름철에 많이 사용하는 직물로 바지를 제작하고 착용시킨후 인체 생리 반응을 분석하여 여름철에 쾌적한 바지를 알아 보았다. 이 연구를 통해 일반인과는 생활 자세가 다른 휠체어를 사용하는 하지 마비자와 일반인이 입는 기성복 바지를 착용 했을 때 생기는 불합리한 요소들을 고려하여 미적이고 기능적 및 위생적인 측면에서 신체 장애자에게 보다 적합한 바지를 제작하기 위한 기초 자료를 제공하고자 한다.값은 $f^{m}$ (p-1)-1 이다. (n=2m)이 많고 흡연 등의 만성 자극 요인이 있으며 술후 음성 호전에 걸리는 기간이 길어 보다 복합적인 측면에서 치료에 임하여야 할 것으로 사료된다. with such configuration.trap with 2.88[eV] deep of injected space charge from the chathode in the crystaline regions. The origin of ${\alpha}$$_2$ peak was regarded as the detrapping process of ions trapped with 0.9[eV] deep originated from impurity-ion remained in the specimen during production process of the material, in the crystalline regions. The origin of ${\beta}$ peak was concluded to be due to the depolarization process of "C=0"dipole with the activation energy of 0.75[eV] in the amorphous regions. The origin of ${\gamma}$ peak was responsible to the process combined with the depolarization of "CH$_3$", chain segment, with the activation

• Journal of Sensor Science and Technology
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• v.18 no.1
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• pp.48-53
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• 2009

$Eu^{2+}$-doped ${SrAl_2}{O_4}$ and $Eu^{2+}$, $Dy^{3+}$ co-doped ${SrAl_2}{O_4}$ phosphors have been synthesized by conventional solid state method. Photocurrent properties of $Eu^{2+}$ doped ${SrAl_2}{O_4}$ and $Eu^{2+}$, $Dy^{3+}$ co-doped ${SrAl_2}{O_4}$ phosphors, in order to elucidate $Dy^{3+}$ co-doping effect, during and after ceasing ultraviolet-ray (UV) irradiation have been investigated. The photocurrent of $Eu^{2+}$, $Dy^{3+}$ co-doped ${SrAl_2}{O_4}$ phosphors during UV irradiation was 4-times lower than that of $Eu^{2+}$-doped ${SrAl_2}{O_4}$ during UV irradiation, and 7-times higher than that of $Eu^{2+}$-doped ${SrAl_2}{O_4}$ after ceasing UV irradiation. The photocurrent results indicated that holes of charge carriers captured in hole trapping center during the UV irradiation and liberated after-glow process, and made clear that $Dy^{3+}$ of co-dopant acted as a hole trap. The photocurrent of ${SrAl_2}{O_4}$ showed a good proportional relationship to UV intensity in the range of $1{\sim}5mW/cm^2$, and $Eu^{2+}$-doped ${SrAl_2}{O_4}$ was confirmed to be a possible UV sensor.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.83-90
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• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.34-37
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• 1992

In this paper, the $(SrPb)(CaMg)TiO_3$-xBi_2O_3{\cdot}3TiO_2$ ceramics with paraelectric properties were fabricated by the mixed oxide method. In order to investigate the behavior of charged particles, the characteristics of electrical conduction and thermally stimulated current were measured respectively. As a result on characteristics of the electrical conduction, the leakage current was increased as measuring temperature was increased. At room temperature, the conduction current was divided into the three steps as a function of DC electric field. The first step was Ohmic region due to ionic conduction, below 15[kV/cm]. The second step was showed a saturation which seems to be related to a depolarizing field occuring in field-enforced ferroelectric phase, between 15[kV/cm] and 40[kV/cm]. The third step was attributed to Child's law related to spare charge which injected from electrode, above 40[kV/cm]. Thermally stimulated currents(TSC) spectra with various biasing fields exhibited three distinguished peaks that were denoted as ${\alpha}$, ${\alpha}'$ and ${\beta}$ peak, each of which appeared at nearby -30, 20 and 95[$^{\circ}C$] respectively. It is confirmed that the a peak was due to trap electron trapped in the grainboundary, and ${\alpha}'$ peak that was observed above only 1.5[kV/mm] was attributed to field-enforced ferroelectric polarization. The origin of ${\beta}$ peak was identified as ion migration which caused the degradation.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.227-230
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• 1990

The addition of titanium has come to produce an increase in the conductivity of ${\alpha}-Fe_2O_3$ and has been shown NTC ( negative temperature coefficient ) characteristics. Titanium enters the ${\alpha}-Fe_2O_3$ lattice substitutionally as $Ti^{4+}$,thus producing an $Fe^{2+}$ and maintaining the average charge per cation at three. Thus the $Fe^{2+}$ acts as a donor center with respect to the surrounding $Fe^{3+}$ ions. The sintering temperature, compacting pressure and sintering tire have an effect on the electrical properties. C-V and other properties have been measured on polycrystalline samples of ${\alpha}-Fe_2O_3$ containing small deviations from stoichiometry and small amounts of added Titanium. This measurment was made in the course of an investigation of the NTC mechanism in oxides whose cations have a partially filled d-level. C-V and frequency properties have been applied to the measurement of the trap barrier properties at the grain boundary. The double Schottky barrier at the grain boundary is the major cause of the NTC mechanism in NTC thermistor of ${\alpha}-Fe_2O_3$ containing N-type impurity.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.71-72
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• 1998

반도체 집적 공정의 발달로 차세대 소자용으로 30 A 이하의 극 박막 Si02 절연막이 요구되고 있으며, 현재 제품으로 50-70 A 두께의 절연막을 사용한 것이 발표되고 있다. 절연막의 두께가 앓아질수록 많은 문제가 발생할 수 있는데 그 예로 절연막의 breakdo때둥에 의한 신뢰성 특성의 악화, 절연막올 통한 direct tunneling leakage current, boron풍의 dopant 침투로 인한 소자 특성 ( (Threshold Voltage)의 불안, 전기적 stress하에서의 leakage current증가와 c charge-trap 및 피terface s쩌.te의 생성으로 인한 소자 특성의 변화 둥으로 요약 된다. 절연막의 특성올 개선하기 위해 여러 가지 새로운 공정들이 제안되었다. 그 예로, Nitrogen올 Si/Si02 계면에 doping하여 절연막의 특성을 개선하는 방법 으로 고온 열처 리 를 NH3, N20, NO 분위 기 에서 실시 하거 나, polysilicon 또는 s silicon 기판에 nitrogen올 이온 주입하여 열처리 하는 방법, 그리고 Plasma분 위기에서 Nitrogen 함유 Gas를 이용하여 nitrogen을 doping시키는 방법 둥이 연구되고 있다. 또한 Oxide cleaning 후 상온에서 성장되는 oxide를 최소화 하여 절연막의 특성올 개선하기 위하여 LOAD-LOCK을 이용하는 방법, C뼈피ng 공정의 개선올 통한 contamination 감소와 silicon surface roughness 감소 로 oxide 신뢰성올 개선하는 방법 둥이 있다. 구조적 인 측면 에 서 는 Polysilicon 의 g없n size 를 최 적 화하여 OxideIPolysilicon 의 계면 특성올 개선하는 연구와 Isolation및 Gate ETCH공정이 절연막의 특성에 미 치 는 영 향도 많이 연구되 고 있다 .. Plasma damage 가 Oxide 에 미 치 는 효과 를 제어하는 방법과 Deuterium열처리 퉁올 이용하여 Hot electron Stress하에서 의 MOS 소자의 Si/Si02 계면의 신뢰성을 개선하고 있다. 또한 극 박막 전연막의 신뢰성 특성올 통계적 분석올 통하여 사용 가능한 수명 올 예 측 하는 방법 과 Direct Tunneling Leakage current 를 고려 한 허 용 가농 한 동작 전 압 예측 및 Stress Induced Leakage Current 둥에 관해서 도 최 근 활발 한 연구가 진행되고 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.470-470
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• 2012

Organic thin film transistors (OTFTs) backplane constitute the active elements in new generations of plastic electronic devices for flexible display. The overall OTFTs performance is largely depended on the properties and quality of each layers of device material. In solution based process of organic semiconductors (OSCs), the interface state is most impediments to preferable performance. Generally, a threshold voltage (Vth) shift is usually exhibited when organic gate insulators (OGIs) are exposed in an ambient air condition. This phenomenon was caused by the absorbed polar components (i.e. oxygen and moisture) on the interface between OGIs and Soluble OSCs during the jetting process. For eliminating the polar component at the interface of OGI, the role of high vacuum seasoning on an OGI for all solution processable OTFTs were studied. Poly 4-vinly phenols (PVPs) were the material chosen as the organic gate dielectric, with a weakness in ambient air. The high vacuum seasoning of PVP's surface showed improved performance from non-seasoning TFT; a $V_{th}$, a ${\mu}_{fe}$ and a interface charge trap density from -8V, $0.018cm^2V^{-1}s^{-1}$, $1.12{\times}10^{-12}(cm^2eV)^{-1}$ to -4.02 V, $0.021cm^2V^{-1}s^{-1}$, $6.62{\times}10^{-11}(cm^2eV)^{-1}$. These results of OTFT device show that polar components were well eliminated by the high vacuum seasoning processes.