• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.328.1-328.1
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• 2014

MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.37-40
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• 2004

SONOS를 이용한 전하트랩형 플래시 메모리를 통상의 0.35um CMOS 공정을 이용하여 제작하였으며 그 구조는 소스를 공통(CSL. Common Source Line)으로 사용하는 NOR형으로 하였다. 기존의 공정을 그대로 이용하면서 멀티 비트 동작을 통한 실질적 집적도 향상을 얻을 수 있다면 그 의미가 크다고 하겠다. 따라서 본 연구에서는CSL-NOR형 플래시 구조에서 멀티 비트을 구현하기위한 최적의 프로그램/소거/읽기 전압 조건을 구하여 국소적으로 트랩된 전하의 분포를 전하펌핑 방법을 이용하여 조사하였다. 또한 이 방법을 이용하여 멀티 비트 동작 시 문제점으로 제시된 전하의 측면확산을 측정하였다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.157-158
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• 2007

Effects of post-metallization anneal (PMA) on interface trap characteristics of Si-$SiO_2$ are studied. The conventional PMA method utilizes forming gas anneal, where 10% hydrogen in nitrogen atmosphere is used. A new PMA method utilizes hydrogen rich PECVD- silicon nitride $(SiN_x)$ film as a hydrogen diffusion source and a out-diffusion blocking layer. It can be shown through charge pumping current measurement that the new PMA is indeed effective to decrease Si-$SiO_2$ interface trap density.

• Journal of Energy Engineering
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• v.28 no.3
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• pp.55-64
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• 2019

This study identified key patents on U.S. underground water technology through patent network analysis. As a result, there were many technologies that used the technology to remove heavy metals to prevent contamination of groundwater. While patents between groundwater technology patents were in charge of intermediaries, the connectivity between groundwater technologies is not high. The patented technologies related to groundwater were largely distinguishable by pumping, monitoring, and decontamination. Monitoring includes techniques that enable identification of physical and biological properties, such as the type of contaminants, as well as geographic characteristics for analysis of groundwater flow, flow or water quality. Pollution purification technology refers to the process of physiochemical and biological purification for soil and groundwater. U.S. technology cases showed that the U.S. had high technology in water treatment area. And patent protection were also needed to cope with water shortages caused by climate change.