• Title/Summary/Keyword: Charge Pump

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Design of a Charge Pump Circuit Using Level Shifter for LED Driver IC (LED 구동 IC를 위한 레벨 시프터 방식의 전하펌프 회로 설계)

  • Park, Won-Kyeong;Park, Yong-Su;Song, Han-Jung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.1
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    • pp.13-17
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    • 2013
  • In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

Phase-Locked Loops using Digital Calibration Technique with counter (카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프)

  • Jeong, Chan-Hui;Abdullah, Ammar;Lee, Kwan-Joo;Kim, Hoon-Ki;Kim, Soo-Won
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.2
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    • pp.320-324
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    • 2011
  • A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

Charge-Pump High Voltage Inverter for Plasma Backlight with Current Injection Method (CIM(Current Injection Method)을 이용한 Charge-Pump 방식의 Plasma Backlight용 고압 Inverter)

  • Jang, Jun-Ho;Kang, Shin-Ho;Lee, Jun-Young
    • Proceedings of the KIPE Conference
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    • 2007.07a
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    • pp.381-383
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    • 2007
  • Charge-pump high voltage inverter for Plasma backlight with CIM(Current Injection Method) is proposed in this paper. Adoption of ERC is a new attempt in high voltage inverter so that it is not only energy recovery but also improvement of discharge stability and system unstability which is interrupted by noise. Using a charge-pump technique enables low voltage switches to be usable, the cost can be reduce. CIM is adopted to achieve high speed energy recovery in proposed circuit. Operations of the proposed circuit are analyzed for each mode. The proposed circuit is verified to be applicable on a 32 inch plasma backlight panel by experimental results.

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Effects of Gas Injection on the Heating Performance of a Two-Stage Heat Pump Using a Twin Rotary Compressor with Refrigerant Charge Amount

  • Heo, Jae-Hyeok;Jeong, Min-Woo;Jeon, Jong-Ug;Kim, Yong-Chan
    • International Journal of Air-Conditioning and Refrigeration
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    • v.16 no.3
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    • pp.77-82
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    • 2008
  • For heat pumps used in a cold region, it is very important to obtain appropriate heating capacity. Several studies using a variable speed compressor and an additional heater have been performed to enhance heating capacity at low ambient temperatures. However, for outdoor temperature conditions below $-15^{\circ}C$, it is still difficult to obtain enough heating capacity above the rated value. In recent studies, the application of gas injection technique into a two-stage heat pump yielded noticeable heating performance improvement at low temperature conditions. In this study, the heating performance of a two-stage gas injection heat pump with a rated capacity of 3.5 kW was measured and analyzed by varying refrigerant charge amount and EEV opening at the standard heating condition. The heating performance of the two-stage gas injection heat pump was compared with that of a two-stage non-injection heat pump. The heating capacity and COP of the two-stage gas injection heat pump were improved by 2-10% at the optimal charging condition over those of the two-stage non-injection heat pump.

Design of the Charge pump PLL using Dual PFD (듀얼 위상 주파수 검출기를 이용한 차지펌프 PLL 설계)

  • Lee, Jun-Ho;Lee, Geun-Ho;Son, Ju-Ho;Kim, Sun-Hong;Yu, Young-Gyu;Kim, Dong-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.20-26
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    • 2001
  • In this paper, the charge pump PLL using the dual PFD to improve the trade-off between acquisition behavior and locked behavior is proposed. This dual PFD consists of a positive edge triggered PFD and a negative edge triggered PFD. The proposed charge pump shows that it is possible to overcome the issue of the charge pump current imsmatch by the current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. The proposed charge pump PLL is simulated by SPICE using 0.25${\mu}m$ CMOS process parameters.

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A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

  • Park, Hyung-Gu;Jang, Jeong-A;Cho, Sung Hun;Lee, Juri;Kim, Sang-Yun;Tiwari, Honey Durga;Pu, Young Gun;Hwang, Keum Cheol;Yang, Youngoo;Lee, Kang-Yoon;Seo, Munkyo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.777-788
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    • 2014
  • This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using $0.18{\mu}m$ BCD process with high power MOSFET options, and the die area is $1870{\mu}m{\times}1430{\mu}m$. The power consumption of the charge pump itself is 79.13 mW when the output power is 415.45 mW at the high voltage mode, while it is 20.097 mW when the output power is 89.903 mW at the low voltage mode. The measured maximum power efficiency is 84.01 %, when the output voltage is from 7.43 V to 12.23 V.

A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique

  • Moon, Yongsam
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.331-338
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    • 2014
  • A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

A DC-DC Converter Design with Internal Capacitor for TFT-LCD Driver IC (TFT -LCD 구동 IC용 커패시터 내장형 DC-DC 변환기 설계)

  • Lim Gyu-Ho;Kang Hyung-Geun;Lee Jae-Hyung;Sohn Ki-Sung;Cho Ki-Seok;Baek Seung-Myun;Sung Kwan-Young;Li Long-Zhen;Park Mu-Hun;Ha Pan-Bong;Kim Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.7
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    • pp.1266-1274
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    • 2006
  • A non-overlap boosted-clock charge pump(NBCCP) with internal pumping capacitor, an advantageous circuit from a minimizing point of TFT-LCD driver IC module, is proposed in this paper. By using the non-overlap boosted-clock swinging in 2VDC voltage, the number of pumping stages is reduced to half and a back current of pumping charge from charge pumping node to input stage is also prevented compared with conventional cross-coupled charge pump with internal pumping capacitor. As a result, pumping current of the proposed NBCCP circuit is increased more than conventional cross-coupled charge pump, and a layout area is decreased. A proposed DC-DC converter for TFT-LCD driver IC is designed with $0.18{\mu}m$ triple-well CMOS process and a test chip is in the marking.

A Charge Pump Design with Internal Pumping Capacitor for TFT-LCD Driver IC (내장형 펌핑 커패시터를 사용한 TFT-LCD 구동 IC용 전하펌프 설계)

  • Lim, Gyu-Ho;Song, Sung-Young;Park, Jeong-Hun;Li, Long-Zhen;Lee, Cheon-Hyo;Lee, Tae-Yeong;Cho, Gyu-Sam;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.10
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    • pp.1899-1909
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    • 2007
  • A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

Design of a Voltage Multipler Circuit using a Modified Voltage Doubler (개선된 배전압 회로를 이용한 전압증배기 회로 설계)

  • Yeo, Hyeop-Goo;Jung, Seung-Min;Sonh, Seung-Il;Kang, Min-Koo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.696-698
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    • 2012
  • This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generate about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

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