• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1593-1599
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• 2017

This paper presents a multi-channel light-emitting diode (LED) driver IC with a current-mode current regulator. The proposed current regulator replaces resistors for current sensing with a sequentially controlled single current sensor and a single regulation loop for sensing and regulating all LED channel currents. This minimizes the current mismatch among the LED channels and increases voltage headroom or, equivalently, power efficiency. The proposed LED driver IC was fabricated in a $0.35-{\mu}m$ BCD 60-V high voltage process, and the chip area is $1.06mm^2$. The measured maximum power efficiency is 93.4 % from a 12-V input, and the inter-channel current error is smaller than as low as ${\pm}1.3%$ in overall operating region.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Journal of Fisheries and Marine Sciences Education
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• v.13 no.2
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• pp.168-177
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• 2001

The flow pattern and water mass structure in the Chungmu channel were investigated using the field observations during June and July, 2001. The currents in the channel may be regarded as a hydraulic current decided by difference of tide levels between two sides in the channel. The strongest current in the channel occurs around in high water and low water. The coefficient C to be determined the characteristics of velocity in the channel was obtained from an equation, $u=C{\sqrt{2gh}}$ and ranges from 0.37 to 0.65 in the Chungmu Channel at the spring tide and from 0.23 to 0.37 at the neap tide. Eastward tidal transport is usually larger than that of westward transport in Chungmu the Channel. Sea water exchange rates are 39.2% in spring tide and 20.5% in neap tide respectively. The water mass structure in the channel is changed by the speed of the tidal current. The water mass is well mixed at the high water when the current is strong and is stratified at slack water when the current is weak.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1617-1622
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• 2015

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.57 no.3
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• pp.214-227
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• 2021

The distribution of tidal current and tidal induced residual current, topographical eddies and tidal residual circulation in the waters surrounding the Geumo Island-An Island channel were identified through numerical model experiments and vorticity balance analysis. Tidal current flows southwest at flood and northeast at ebb along the channel. The maximum flow velocity was about 100-150 cm/s in neap and spring tide. During the flood current in the neap tide, clockwise small eddies were formed in the waters west of Sobu Island and southwest of Daebu Island, and a more grown eddy was formed in the southern waters of Geumo Island in the spring tide. A small eddy that existed in the western waters of Chosam Island during the ebb in neap tide appeared to be a more grown topographical eddy in the northeastern waters of Chosam Island in spring tide. Tidal ellipses were generally reciprocating and were almost straight in the channel. These topographical eddies are made of vorticity caused by coastal friction when tidal flow passes through the channel. They gradually grow in size as they are transported and accumulated at the end of the channel. When the current becomes stronger, the topographic eddies move, settle, spread to the outer sea and grow as a counterclockwise or clockwise tidal residual circulation depending on the surrounding terrain. In the waters surrounding the channel, there were counterclockwise small tidal residual circulations in the central part of the channel, clockwise from the northeast end of the channel to northwest inner bay of An Island, and clockwise and counterclockwise between Daebu Island and An Island. The circulation flow rate was up to 20-30 cm/s. In the future, it is necessary to conduct an experimental study to understand the growth process of the tidal residual circulation in more detail due to the convergence and divergence of seawater around the channel.

• Journal of IKEEE
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• v.27 no.4
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• pp.399-404
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• 2023

In this paper, we analyzed the current path in the O/N/O (Oxide/Nitride/Oxide) structure of 3D NAND Flash memory and in the O/N/F (Oxide/Nitride/Ferroelectric) structure where the blocking oxide is replaced by a ferroelectric. In the O/N/O structure, when V_read is applied, a current path is formed on the backside of the channel due to the E-fields of neighboring cells. In contrast, the O/N/F structure exhibits a current path formed on the front side due to the polarization of the ferroelectric material, causing electrons to move toward the channel front. Additionally, we performed an examination of device characteristics considering channel thickness and channel length. The analysis results showed that the front electron current density in the O/N/F structure increased by 2.8 times compared to the O/N/O structure, and the front electron current density ratio of the O/N/F structure was 17.7% higher. Therefore, the front current path is formed more effectively in the O/N/F structure than in the O/N/O structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1311-1316
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• 2016

This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.4
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• pp.612-616
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• 2012

This paper presents an active current regulator for LED driver IC. The proposed driver circuit is consists of DC-DC converter for supplying constant DC voltage to LED, active current regulator for compensating channel-to-channel current error from LED strings and feedback circuit for controlling duty ratio of the converter. The proposed active current regulator senses current of LED channels by equalizing both $V_{DS}$ and $V_{GS}$ at LED current control transistor. Because the proposed circuit directly measures the LED channel current without a sensing resistor and regulates all channel with same regulation loop, the power consumption and the current error are much small compared with previous works. The measured maximum efficiency of overall LED driver IC is approximately 94% and current error of LED channel-to-channel is under ${\pm}1.3%$. The proposed LED driver IC is fabricated Dongbu 0.35um BCD process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.992-997
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• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.