• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.333-334
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• 2008

With the role of cell phones in today's society as a digital personal assistant as well as the primary tool for personal communication, it is possible to imagine the involvement of cell phones in almost any type of crime. The progression of a criminal investigation can hinge on vital clues obtained from a cell phone. This paper will be concentrated on CDMA system phones and focus on the data extraction for cell phone forensics. Especially, the data acquisition method of JTAG interface access to memory chip will be covered.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.140-142
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• 2003

We have designed a SFQ (Single Flux Quantum) D2 Cell and Inverter(NOT) for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we have used Julia, XIC and Lmeter for simulations and layouts. We obtained the circuit margin of larger than $\pm$25%. After layout, we drew chip for fabrication of SFQ D2 Cell and Inverter. We connected D2 Cell and Inverter to jtl, DC/SFQ, SFQ/DC and RS flip-flop for measurement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• BT NEWS
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• v.17 no.2
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• pp.54-57
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• 2010

• The Magazine of the IEIE
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• v.29 no.3
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• pp.36-40
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• 2002

• Design & Manufacturing
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• v.15 no.2
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• pp.11-16
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• 2021

Recently, three-dimensional (3D) cell culture systems, which are superior to conventional two-dimensional (2D) vascular systems that mimic the in vivo environment, are being actively studied to reproduce drug responses and cell differentiation in organisms. Conventional two-dimensional cell culture methods (scaffold-based and non-scaffold-based) have a limited cell growth rate because the culture cannot supply the culture medium as consistently as microvessels. To solve this problem, we would like to propose a 3D culture system with an environment similar to living cells by continuously supplying the culture medium to the bottom of the 3D cell support. The 3D culture system is a structure in which microvascular structures are combined under a scaffold (agar, collagen, etc.) where cells can settle and grow. First, we have manufactured molds for the formation of four types of microvessel-mimicking chips: width / height ①100 ㎛ / 100 ㎛, ②100 ㎛ / 50 ㎛, ③ 150 ㎛ / 100 ㎛, and ④ 200 ㎛ / 100 ㎛. By injection molding, four types of microfluidic chips were made with GPPS (general purpose polystyrene), and a 100㎛-thick PDMS (polydimethylsiloxane) film was attached to the top of each microfluidic chip. As a result of observing the flow of the culture medium in the microchannel, it was confirmed that when the aspect ratio (height/width) of the microchannel is 1.5 or more, the fluid flows from the inlet to the outlet without a backflow phenomenon. In addition, the culture efficiency experiments of colorectal cancer cells (SW490) were performed in a 3D culture system in which PDMS films with different pore diameters (1/25/45 ㎛) were combined on a microfluidic chip. As a result, it was found that the cell growth rate increased up to 1.3 times and the cell death rate decreased by 71% as a result of the 3D culture system having a hole membrane with a diameter of 10 ㎛ or more compared to the conventional commercial. Based on the results of this study, it is possible to expand and build various 3D cell culture systems that can maximize cell culture efficiency by cell type by adjusting the shape of the microchannel, the size of the film hole, and the flow rate of the inlet.