• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1506-1511
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• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.379-382
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• 2013

In conventional solar energy harvesting systems, continuous perturbation techniques of the duty cycle or switching frequency of a power converter have been used to implement MPPT(Maximum Power Point Tracking) control. In this paper, we propose a new MPPT technique to control the duty cycle of a power switch powering a power converter. The proposed circuit is designed in 0.35um CMOS process, and the designed chip area including pads is $770um{\times}800um$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2407-2409
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• 2005

본 논문에서는 다양한 생물분자 감지를 위한 센서로 마이크로캔틸레버를 제안하였고 이것을 이용해 여러 생물 분자들을 광학적, 전기적으로 분석하였다. 마이로캔틸레버는 표면 미세 가공 기술로 제작되었고, 이러한 제작 방식은 공정이 간단하고 비용이 적게 들며 센서 array가 가능하다는 장점을 갖는다. 생물분자를 포함하는 용액을 주입하기 위하여 PDMS와 fused silica glass를 이용해 fluid cell system을 제작하였다. 마이크로캔틸레버 상단의 gold가 코팅된 부분에서 생물분자의 자기조립 (self assembly)현상이 일어나고 이는 마이크로캔틸레버 상, 하단의 표면 스트레스 차이를 야기 시킨다. 이로 인해 마이크로캔틸레버 자체의 휘어짐 현상이 일어나게 되고 이러한 휘어진 정도를 측정함으로써 마이크로캔틸레버의 생물분자 감지능을 확인할 수 있었다. Cystamine dihydrochloride와 glutaraldehyde 분자를 분석하였고 각기 다른 농도의 cystamine dihydrochloride 용액에서도 실험함으로써 농도별 감지능 또한 확인하였다. 이러한 생물분자 감지를 위한 마이크로캔틸레버의 센서로써의 성능은 u-TAS 와 lab-on-a-chip에서 유용히 이용될 수 있으리라 확신한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.181-189
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• 2001

In this thesis, a policing algorithm is proposed, which is one of the traffic management function in ATM networks. The proposed algorithm minimizes CLR(Cell Loss patio) of high priority cells and solves burstiness problem of the traffic caused by multiplexing and demultiplexing process. The proposed algorithm has been implemented with VHDL and is divided into three parts, which are an input module, an UPC module, and an output module. In implementation of the UPC module\`s memory access, memory address is assigned according to VCI\`s LSB(Lowest Significant Byte) of ATM header for convenience. And the error of VSA operation from counter\`s wrap-around can be recovered by the proposed method. ANAM library 0.25 $\mu\textrm{m}$ and design compiler of Synopsys are used for synthesis of the algorithm and Synopsys VSS tool is used for VHDL simulation of it

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.414-417
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• 2008

This paper presents the design and analysis of 2.45GHz Low-IF Mixer using CMOS 0.18um. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique, and the resonating technique for the tail capacitance. And the design of this Double Balance Mixer is based on its lineaity since it is important in the interference cancellation system. The low flicker noise mixer is implemented by incorporating a double balanced Gilber-type configuration, the RF leakage-less current bleeding technique, and Cp resonating technique. The proposed mixer has a simulated conversion gain of 16dB a simulated IIP3 of -3.3dBm and P1dB is -19dBm. A simulated noise figure of 6.9dB at l0MHz and a flicker corner frequency of 510kHz while consuming only 10.65mW od DC power. The layout of Mixer for one-chip design in a 0.18-um TSMC process has 0.474mm$\times$0.39 mm size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1835-1839
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• 2008

Power management is a very important issue in portable electronic applications. Portable electronic devices require very efficient power management like LDO to increase the battery life. As the voltage variation of battery power is large in the application of cell phone, camera, laptop, automotive, industry application and so on, battery power is not directly used and LDO is used to supply the power of internal circuit. Besides, LDO can supply DC voltage that is lower than bauer voltage and constant DC voltage that is not related to largely fluctuated battery power. In the study, the power-save mode current and IR-drop characteristics are analyzed from a LDO with on-chip fabricated in 0.18-um CMOS technology.