• Journal of Korean Society of Industrial and Systems Engineering
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• 제28권2호
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• pp.94-100
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• 2005

This paper presents the application of integrated mathematical programming approach for the design of cellular manufacturing. The proposed approach is carried out in two phases The first phase concerning exceptional elements(EEs) in cell formation and the second phase facilities layout design. This paper considers the total costs of three important costs for (1) intercellular transfer (2) machine duplication and (3) subcontracting. One of Important issue is the calculation of the number of machines considering the maximum utilization of machines and the available capacity of a machines that can be transferred between cells. Facilities layout design is considered to reflect the real field data taking in to account the operational sequence of the parts to be manufactured. The model is formulated as mixed integer programming that is employed to find the optimal solution.

• Industrial Engineering and Management Systems
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• 제8권1호
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• pp.22-28
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• 2009

We consider facility layout problems, where mn facility units are assigned into mn cells. These cells are arranged into a rectangular pattern with m rows and n columns. In order to solve this cell type facility layout problem, many approximation algorithms with improved local search methods were studied because it was quite difficult to find exact optimum of such problem in case of large size problem. In this paper, new algorithms based on Simulated Annealing (SA) method with two neighborhood generation methods are proposed. The new neighborhood generation method adopts the exchanging operation of facility units in accordance with adjacent preference. For evaluating the performance of the neighborhood generation method, three algorithms, previous SA algorithm with random 2-opt neighborhood generation method, the SA-based algorithm with the new neighborhood generation method (SA1) and the SA-based algorithm with probabilistic selection of random 2-opt and the new neighborhood generation method (SA2), are developed and compared by experiment of solving same example problem. In case of numeric examples with problem type 1 (the optimum layout is given), SA1 algorithm could find excellent layout than other algorithms. However, in case of problem type 2 (random-prepared and optimum-unknown problem), SA2 was excellent more than other algorithms.

• Journal of the Korean Institute of Telematics and Electronics
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• 제24권6호
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• pp.1049-1055
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• 1987

This paper describes a near-optimal standard cell layout strategy which consists of three consecutives steps` partition, placement, and routing. In the partition step, a given network is torn apart into many subnetworks such that each subnetworks contains as many cells as possible with minimum interocnnections between subnetwork. In the placement step, the conventional string placement algorithm was modified. Also, bonding pads were placed such that their connections to the related cells are shortest. As a result for the tested example, the placement time was saved by 60% and the total routing lengths were saved by more than 20% and substantial improvements in the number of feed-through cell and the track density were obtained. The layout program is coded in PASCAL and implemented on a VAX 11-750/UNIX computer.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 한국초전도저온공학회 2003년도 학술대회 논문집
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• pp.140-142
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• 2003

We have designed a SFQ (Single Flux Quantum) D2 Cell and Inverter(NOT) for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we have used Julia, XIC and Lmeter for simulations and layouts. We obtained the circuit margin of larger than $\pm$25%. After layout, we drew chip for fabrication of SFQ D2 Cell and Inverter. We connected D2 Cell and Inverter to jtl, DC/SFQ, SFQ/DC and RS flip-flop for measurement.

• Communications for Statistical Applications and Methods
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• 제7권1호
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• pp.119-128
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• 2000

This paper proposes a method for detecting interactions in a two-way layout with one observation per cell. The identification of interactions in the model is not clear for they are confounding with error terms. The $L_1$-Estimation is robust with respect to a y-direction outlier in linear model so we are able to estimate main effects without affection of interactions, If an observation is classified as an outlier we conclude it contains an interaction. An empirical study compared with a classical method is performed.

• ETRI Journal
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• 제26권6호
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Korean Operations Research and Management Science Society
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• 제18권3호
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• pp.159-177
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• 1993

One of major research issues in cellular manufacturing is studing factors that are fovorable or detrimental to the conversion of traditional functional layouts to GT cellular layouts. Among many factors, this paper explored plausible relationships between the scope of plant conversion and the manufacturing cell design processes and outcomes. The cell design practices of 28 U. S. plants were surveyed through a mail questionaire. While most relationships were not statistically significant, some interesting findings and insights could be drawn. With this researhc, we can better understand a part of relationships between the company's conversion strategy and the cell design strategies and outcomes.

• Proceedings of the KIEE Conference
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1463-1466
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• 1987

The problem of generating minimal area CMOS functional cell layout can be converted to that of decomposing the transistor connection graph into a minimum number of subgraphs, each having a pair of Euler paths with the same sequence of input labels on the N-graph and P-graph, which are portions of the graph corresponding to NMOS and PMOS parts respectively. This paper proposes a heuristic algorithm which yields a nearly minimal number of Euler paths from the path representation formula which represents the give a logic function. Subpath merging is done through a list processing scheme where the pair of paths which results in the lowest cost is successively merged from all candidate merge pairs until no further path merging and further reduction of number of subgraphs are possible. Two examples were shown where we were able to further reduce the number of interlaces, i.e., the number of non-butting diffusion islands, from 3 to 2, and from 2 to 1, compared to the earlier work [1].

• Journal of information and communication convergence engineering
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• 제2권4호
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• pp.209-213
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• 2004

With the commercialization of CDMA 2000-1x late in 2000, a high-speed wireless Internet, based on a mobile communication networks, appeared in Korea. This will develop into the next-generation of mobile communications(4G) in the future and the new cell layout will be required the cellular configuration of 4G. We would need the legislation with respect to base-stations and to building the mobile communication networks, as well as the optimization of mobile communication systems. In this study, in order to provide 4G, I examined and analyzed that the current laws & regulations related to licensing and operating a mobile communication base-stations in KOREA.

• Journal of the Korean Institute of Telematics and Electronics
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• 제24권1호
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• pp.149-158
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• 1987

This paper describes the SEAS which is a 2-dimensional graphic editor for schematic circuit and IC mask layout. This system runs on general purpose computer and Tektronix 4110 series graphic terminal. With this system, user can edit schematic circuits and/or IC mask layout with 2 level hierarchy. This system supports more than 20 kinds of built-in symbol, user definable internal symbols, 60 macros, 16 function keys, 4 level on-screen menu operation and edit-in-place of cell in main drawing. And it provides editing functions such as reflection, rotation, move and copy of one or a group of elements, and modification of polygona geometry etc. To improve the excution speed, we used local memory of graphic terminal. For the portability of the program, the system is written in FORTRAN 77 programming language.