• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1349-1354
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• 2011

In this work, we fabricated the CdZnS/CdTe heterojunction and investigated the C-V characteristics to determine the depletion width and the charge density distribution. A parallel experiment on CdS/CdTe heterojunction was also carried out for comparison. The depletion region width, for CdZnS/CdTe heterojunction, was nearly constant, regardless of bias voltage. However, the depletion region was wider than that of CdS/CdTe heterojunction due to high resistivity of CdZnS film. The interface charge density of CdZnS/CdTe heterojunction was increased linearly with the bias voltage and showed lower values than those for CdS/CdTe junction. The open circuit voltage of CdZnS/CdTe heterojunction solar cells increased with zinc mole ratio due to reducing of the electron affinity difference between CdZnS and CdTe films. However, the increase of series resistance due to the high resistivity of Cd1-xZnxS films results in reducing conversion efficiency.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.106.2-106.2
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• 2011

다층 박막 구조로 이루어진 CdS/CdTe 태양전지의 경우, 각각의 박막이 다양한 제조 공정을 거치면서 물성특성의 변화를 겪게 된다. 각각의 박막이 고온의 열처리 공정과, $CdCl_2$ 용액 처리 및 후면 산화막 제거 공정 등을 거치게 되면서 겪게 되는 물성 변화 분석을 살펴보고자 한다. 각각의 박막 제조 방식은 일반적으로 사용되는 방식으로, CdS의 경우는 용액성장법(Chemical Bath Deposition, CBD), CdTe의 경우는 근접승화법(Closed Space Sublimaition, CSS)을 사용했으며, X-Ray Diffractometer (XRD), Raman spectroscopy, Field Emission Scanning Electron Microscope (FE-SEM), Energy Dispersive Spectroscopy (EDS), X-ray Photoelectron Spectroscopy (XPS) 등을 이용하여 분석하였다. 각각의 셀 제조 공정을 거치면서 CdS, CdTe 박막들은 결정, 광 특성, 성분 변화를 보였다.

• Korean Journal of Materials Research
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• v.8 no.6
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• pp.493-498
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• 1998

CdTe films were deposited by close spaced sublimation with various substrate temperatures, cell areas, and thicknesses of CdTe and ITO layers and their effects on the CdS/CdTe solar cells were investigated. The resistivity of CdTe layers employed in this study was 3$\times$ $10^{4}$$\Omega$cm For constant substrate temperature the optimum substrate ternperature for CdTe deposition was $600^{\circ}C$. To obtain larger grain size and more compact microstructure, CdTe film was initially deposited at 62$0^{\circ}C$, and then deposited at 54$0^{\circ}C$. The CdTe film was annealed at 62$0^{\circ}C$ and $600^{\circ}C$ sequentially to maintain the CdTe film quality. The photovoitaic cell efficiency improved by the "two-wave" process. For constant substrate temperature, the optimum thickness for CdTe was 5-6$\mu m$. Above 6$\mu m$ CdTe thickness, the bulk resistance of CdTe film degraded the cell performance. As the cell area increased the $V_{oc}$ remained almost constant, while $J_{sc}$ and FF strongly decreased because of the increase of lateral resistance of the ITO layer. The optimum thickness of the ITa layer in this study was 300~450nm. In this experiment we obtained the efficiency of 9.4% in the O.5cm' cells. The series resistance of the cell should be further reduced to increase the fill factor and improve the efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1647-1652
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• 2010

A CdS film has been used as a window layer in CdTe and Cu(In,Ga)$Se_2$ thin films solar cell. Partial substitution of Zn for Cd increases the photocurrent and the open-circuit voltage by providing a match in the electron affinities of the two materials and the higher band gap. In this paper, CdZnS/CdTe and CdS/CdTe heterojunctions were fabricated and the electrical characteristics were investigated. Current-voltage-temperature measurements showed that the current transport for CdS/CdTe heterojunction was controlled by both tunneling and interface recombination. However, CdZnS/CdTe heterojunction displayed different current transport mechanism with the operating temperature. For above room temperature, the current transport of device was generation/recombination in the depletion region and was the leakage current and/or tunneling in the range below room temperature.

• Solar Energy
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• v.11 no.3
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• pp.74-83
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• 1991

In this study, the (p)ZnTe/(n)Si solar cell and (n)CdS-(p)ZnTe/(n)Si poly-junction thin film are fabricated by vaccum deposition method at the substrate temperature of $200{\pm}1^{\circ}C$ and then their electrical properties are investigated and compared each other. The test results from the (p)ZnTe/(n)Si solar cell the (n)CdS-(p)ZnTe/(n)Si poly-junction thin fiim under the irradiation of solar energy $100[mW/cm^2]$ are as follows; Short circuit current$[mA/cm^2]$ (p)ZnTe/(n)Si:28 (n)CdS-(p)ZnTe/(n)Si:6.5 Open circuit voltage[mV] (p)ZnTe/(n)Si:450 (n)CdS-(p)ZnTe/(n)Si:250 Fill factor (p)ZnTe/(n)Si:0.65 (n)CdS-(p)ZnTe/(n)Si:0.27 Efficiency[%] (p)ZnTe/(n)Si:8.19 (n)CdS-(p)ZnTe/(n)Si:2.3 The thin film characteristics can be improved by annealing. But the (p)ZnTe/(n)Si solar cell are deteriorated at temperatures above $470^{\circ}C$ for annealing time longer than 15[min] and the (n)CdS-(p)ZnTe/(n)Si thin film are deteriorated at temperature about $580^{\circ}C$ for longer than 15[min]. It is found that the sheet resistance decreases with the increase of annealing temperature.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.05a
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• pp.32-32
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• 1999

• JOURNAL OF ELECTRICAL WORLD
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• no.4 s.148
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• pp.22-29
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• 1989

• Electrical & Electronic Materials
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• v.10 no.9
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• pp.930-937
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• 1997

Polycrystalline CdTe thin films have been studied for photovoltaic application because of their high absorption coefficient and optimal band energy(1.45 eV) for solar energy conversion. In this study CdTe thin films were deposited on CdS(chemical bath deposition)/ITO(indium tin oxide) substrate by rf-magnetron sputtering under various conditions. Structural optical and electrical properties are investigated with XRD UV-Visible spectrophotometer SEM and solar simulator respectively. The fabricated CdTe/CdS solar cell exhibited open circuit voltage( $V_{oc}$ ) of 610 mV short circuit current density( $J_{sc}$ ) of 17.2 mA/c $m^2$and conversion efficiency of about 5% at optimal sputtering conditions.

• Electrical & Electronic Materials
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• v.1 no.1
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• pp.26-34
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• 1988

Sintered CdS/CdTe solar cells have been farbricated by coating a (Cd+Te) slurry on sintered CdS films followed by the sintering at 625.deg.C for one hour with various heating rates. When cadmium and tellurinm powders are used instead of CdTe powder to form CdS/CdTe junction, CdTe is formed in the temperature range of 290.deg.C-400.deg.C. The microstructure of the CdTe films depends strongly on the heating rate of the sintering due to the low melting temperature and the high vapor pressure of the elemental Cd and Te. An optimum heating rate obtain CdTe films with uniform and dense microstructure which, in turn, improves the efficiency of the sintered CdS/CdTe solar cells. All-polycrystalline CdS/CdTe solar cells with an efficiency of 9.57% under 50mW/cm$^{2}$ tungsten light have been farbricated by using a heating rate of 14.deg.C/min.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.27-27
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• 2010

결정성과 전하 이동도가 우수한 CdTe 박막을 증착하기 위하여 근접승화법(CSS), chemical spraying법, 전착(electrodeposition)법, screen printing법, 화학기상증착(MOCVD)법 및 sputtering법등이 응용되고 있으며 이들 방법은 각기 다양한 장단점을 가지고 있다. CdTe 태양전지를 성장시키는 다양한 방법 중에서 본 발표는 CBD를 이용한 CdS와 CSS를 이용한 CdTe 박막 태양전지를 성장하는 방법을 포함한다. 다양한 조건에서 성장된 박막의 물성과 CdCl2와 열처리를 통한 성능개선에 대해 발표할 예정이다. 또한, 공기의 index와 박막의 index 차이가 크기 때문에, escape cone의 angle이 매우 작고, 박막의 경우 표면이 비교적 평평하기 때문에, 광소자(LED와 Solar Cell)는 표편 텍스처링이 성능을 향상시키기 위해 필요하다. Natural Lithography, Wet-etching, Dry-etching, index-grading을 이용하여, LED와 태양전지에서 uniform하고 대면적에 적용가능한 표면 택스처링 방법에 대해 발표할 예정이다.