• ETRI Journal
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• 제38권1호
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• ETRI Journal
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• 제39권1호
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• pp.62-68
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• 2017

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.

• 전기전자학회논문지
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• 제26권4호
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• pp.553-559
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• 2022

본 논문에서는 cascode GaN FET의 하프 브릿지 구성에서 오실레이션 억제를 위한 RC 스너버 회로 설계 기술을 분석한다. 대표적인 WBG 소자인 cascode GaN FET는 우수한 고속 스위칭 특성이 우수하다. 다만, 이러한 고속 스위칭 특성으로 인하여 false turn-off 문제가 야기되며, 이를 억제하기 위해 RC 스너버 회로가 필수적이다. 따라서, 일반적으로 많이 사용되는 실험 기반의 선정 기법과 근궤적법을 이용한 분석 기법을 비교한다. 일반적인 방법의 경우 실험적 경험을 바탕으로 오실레이션 억제 성능이 만족될 때까지 지속적인 회로 변경이 필요하다. 하지만, 근궤적 기법의 경우 비진동 R-C 맵을 기반으로 초기값을 설정 할 수 있다. 이러한 설계 기술에 따른 성능을 비교하기 위해 모의실험과 실제 더블 펄스 회로 구성을 통한 실험을 진행하였다.

• 전자공학회논문지D
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• 제35D권4호
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• pp.1-8
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• 1998

An MMIC single-balanced upconverting mixer for PCS application has been successfully developed using an MMIC process employed by 1 .mu. ion implanted GaAs MESFET and passive lumped elements consisting of spiral inductor, Si3N4 MIM capacitors and NiCr resistors. The configuration of the mixer presented in this paper is two balanced cascode FET mixers with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit including two active baluns intermodulation characteristic with two-tone excitation are also measured, showing -28.17 dBc at IF power of -30 dBm.