• ETRI Journal
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• v.28 no.3
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• pp.275-281
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• 2006

A very simple and efficient scheme for jitter reduction is proposed for a carrier frequency recovery loop using phase differential frequency estimation, which estimates the current frequency offset based on the difference of the average phases of two successive intervals. Analytical and numerical results presented in this paper show that by simply overlapping the observation intervals by half for frequency offset estimations, both the steady-state and transient performances can be improved. The proposed scheme does not require any additional hardware circuitry, but results in improved performance even with reduced complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.2
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• pp.78-85
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• 2002

We introduce a rotational decision-directed joint algorithm of blind equalization coupled with carrier recovery for 32-QAM demodulation with high symbol rate. The proposed carrier recovery, which we call a rotational decision-directed carrier recovery(RDDCR), removes the residual phase difference by rotating the decision boundary for the kth received symbol by the frequency detector output of the (k-1)th received symbol. Since the RDDCR includes the function of PLL loop filter by rotating the decision boundary, it gives a simpler demodulator structure. The rotational decision-directed blind equalization(RDDBE) with the rotated decision boundary based on the Stop-and-Go Algorithm(SGA) operated during tracking the frequency offset by the RDDCR and removes intersymbol interference due to multipaths and channel noise. Test results show that symbol error rate of $10^{-3}$ is obtained before the forward error correction when SNR equals 15dB with 150KHz of carrier frequency offset and two multipaths, which is the channel condition for 32-QAM receiver.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1993.10a
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• pp.570-574
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• 1993

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.226-230
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• 2000

In this paper, we implemented the QPSK demodulator with a CPLD chip, and examined the results. DD(Decision Directed)-Gardner algorithm is used for STR loop and Decision-Directed algorithm is used for CPR loop. The speed of the QPSK demodulator implemented in FLEX10K chip can be guaranteed approximately 2[Mbpsl] transmission speed. In practical designed by ASIC, the speed is faster than that of CPLD by 5-6 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1777-1786
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• 1996

This paper describes theories and implementation techniques of a digital high-definition television(HDTV) modem based on 32-QAM for terrestrial broadcasting. We proposed a digital demodulation scheme and a symbol timing recovery structure based on the band edge component maximization(BECM) method. The adaptive equalizer has 256 complex taps to remove the multipath of delays ranging from -2.mu.s~+24.mu.s with a new T/2-spaced blind equalization algorithm. computer simulation results reveal that the proposed algorithm outperforms other conventional blind equalization algorithm a digital HDTV modem with 4.91MHz symobol rate is implemented by utilizing the proposed algorithms. All processings for modem operations such as demodulation, estimation of symbol timing phase error, adaptive equalization, and carrier recovery except IF signal processing and sampling phase control part of the AD converter are done in digital domain. Especially, the carrier recovery loop can track a carrier offset of upto .+-.350KHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.737-746
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• 1996

In this paper, we present simulation result of quantization effects about a new Angular From Carrier Recovery Loop(AF CR loop) for PSK modulation technique. AF CR loop includes detected angle symbol and Multi Level hardimiter. In general, detected angle is used in dtermining symbol. Because detected angle is used to make an error signal of phase detector output, hardware implementation of AF CR loop is simpler than that of other loops. Before hardware implementation of AF CR loop, the result due to quantization effect should be investigated. In order to confirm quntization effect of AF CR loop, we evaluate performance of this loop by Monte-Carlosimulation method. Under both in the AWGN and Jake's fading noise channel environments, we confirmed the characteristics of AF CR loop in terms of RMS jitter due to quntization effect. Differential APSK modulation schemeis used in this paper. Especially, Jake's fading channel is used as a channel model and also AGC(Automatic Gain Control) is used in the overall process of performance evaluation. We obtained the resonable result of quantization effect about AF CR loop. With the result of performanceevaluation based on quantization effects, we can expect to operate AF CRloop under the fading channel environments reasonably well.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1028-1035
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• 1999

To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.