• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.4
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• pp.268-272
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• 2019

A lithium polymer battery-based 9 kJ/s high-voltage capacitor charger, which comprises two stages, is proposed. A modified LCC resonant converter and resonant circuit are introduced at the first and second stages, respectively. In the first stage, the methods for handling low-voltage and high-current batteries are considered. Delta-wye three-phase transformers are used to generate a high output voltage through the difference between the phase and line-to-line voltages. Another method is placing the series resonant capacitor of the LCC resonant components on the transformer secondary side, which conducts considerably low current compared with the transformer primary side. On the basis of the stable operation of the first charging stage, the secondary charging stage generates final output voltage by using the resonance. This additional stage protects the rectifying diodes from the negative voltage when the output capacitor is discharged for a short time. The inductance and capacitance of the resonance components are selected by considering the resonance charging time. The design procedure for each stage with the aforementioned features is suggested, and its performance is verified by not only simulation but also experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.62-71
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• 2002

An intergral C-V converter is proposed to solve the nonlinearity problem of capacitive pressure sensors. The integral C-V converter consists of a switched-capacitor integrator and a switched-capacitor differential amplifier. It converts the sensor capacitance change which is inversely proportional to an applied pressure into a linear voltage output. Various PSPICE simulations prove that the convertor has excellent characteristics, such as low nonlinearity less than 0.01%/FS and low sensitivity to parallel offset capacitance and parasitic capacitance for the displacement range of sensor diaphragm set to 0 ${\sim}$ 90% of the initial distance between the electrodes in the simulation. We also show that the offset compensation and the gain trimming are easily achieved with the integral C-V converter.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.372-376
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• 2010

Electrolytic capacitors have been widely used in power electronics system because of the features of large capacitance, small size, high-voltage, and low-cost. Electrolytic capacitors, which is most of the time affected by aging effect, plays a very important role for the power electronics system quality and reliability. Therefore it is important to estimate the parameter of an electrolytic capacitor to predict the failure. The estimation of the equivalent series resistance(ESR) is important parameter in life condition monitoring of electrolytic capacitor. This paper proposes a simple technique to measure the ESR of an electrolytic capacitor. This method uses a switching DC/DC boost converter to measure the DC Bus capacitor ESR of power converter. Main advantage of the proposed method is very simple in technique, consumes very little time and requires only simple instruments. Simulation results are shown to verify the performance of the proposed method.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.650-654
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• 1999

In this paper, author describe the simulation results concerning the period doubling bifurcation route to chaos of DC/DC boost converter under current mode control to show that it is common phenomena on switching regulator when parameters are improperly chosen or continuously varied beyond the ensured region by system designer. Bifurcation diagrams of periodic orbits of inductor current and capacitor voltage of DC/DC boost converter are plotted with sampled data at moment of each clock pulse causing switching on. DC/DC boost converter studied on this paper is modelled by its state space equations as per switching condition under continuous conduction mode. Current reference signal and capacitance are chosen as the bifurcation parameters and those are varied in step for iterative calculation to find bifurcation points of periodic orbits of state variables.

• Journal of Power Electronics
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• v.19 no.4
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.221-224
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• 2012

This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.140-149
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• 2017

This study proposes a new type of active-clamp forward-flyback converter with two transformers that operate in forward and flyback modes during on and off times, respectively, instead of not using an output inductor. The main switch can be turned on with zero-voltage switching (ZVS) using the leakage inductance of the transformer and the output capacitor of the main switch. The leakage inductance should be increased to ZVS. However, the ringing between the leakage inductance of the transformer and the parasitic output capacitance of the secondary side rectifier switches results in a serious voltage spike. A forward-flyback converter employing auxiliary inductor and auxiliary diode is proposed to overcome the problem. The operational principles are analyzed in detail and validated through experiments with a 385 V-to-53 V/37 A prototype.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.11
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• pp.156-163
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• 1997

Recently, the three phase AC to DC boost converter has become one of the most widely used power converters as DC power source in the industry applications. In this paepr, a three phase PWM AC toDC boost converter that operates with unity power factor and sinusodial input currents is presented. The current control of the converter is based onthe predicted current control strategy with fixed switching frequency and the input current tracks the reference cuent within one sampling time interval. Therefore, by using this control strategy low ripples in the output voltage, low harmonics in the input current and fast dynamic responses are achieved with a small capacitance in the DC link.

• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.