• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.139-141
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• 2019

Capacitive power transfer has an advantage in the simplicity of the energy link structure. So, the conventional phase -shift full bridge sometime is not always the best choice because of its complexity and high cost. On the other hand, the link capacitance is usually very low and requires high-frequency operation, but, the series resonant converter loses zero-voltage switching feature in the light load condition, which makes the switching loss high especially in CPT system. The paper proposes a new low-cost topology based on asymmetric half-bridge to achieve simplicity as well as wide zero voltage switching range. The design procedure is presented, and circuit operations are analyzed and verified by simulation.

• Journal of Power Electronics
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• v.16 no.3
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• pp.823-831
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• 2016

A high-efficiency method is proposed to suppress magnetic core imbalance in phase-shifted full-bridge (PSFB) converters. Compared with conventional solutions, such as controlling peak current mode (PCM) or adding DC blocking capacitance, the proposed method has several advantages, such as lower power loss and smaller size, because the additional current sensor or blocking capacitor is removed. A time domain model of the secondary side is built to analyze the relationship between transformer core imbalance and cathode voltage of secondary side rectifiers. An approximate control algorithm is designed to achieve asymmetric phase control, which reduces the effects of imbalance. A 60 V/15 A prototype is built to verify the proposed method. Experimental results show that the numerical difference of primary side peak currents between two adjacent cycles is suppressed from 2 A to approximately 0 A. Meanwhile, compared with the PCM solution, the efficiency of the PSFB converter is slightly improved from 93% to 93.2%.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.103-107
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• 2021

In this paper, a capacitive water level sensor for boilers was developed. In order to accurately monitor the water level in a high-temperature boiler that generates a lot of precipitates, the occurrence of precipitates on the surface of the water level sensor should be small, and a sensor capable of measuring even if the sensor surface is somewhat contaminated is required. The capacitive water level sensor has a structure in which one of the two electrodes is insulated with Teflon coating, and the stainless steel package of the water level sensor is brought into contact with the water tank so that the entire water tank becomes another electrode of the water level sensor. A C-V converter that converts the capacitance change of the capacitive water level sensor into a voltage change was developed and integrated with the water level sensor to minimize noise. The performance of the developed capacitive water level sensor was evaluated through measurement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.83-91
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• 2014

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a charge-storing capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and $230{\mu}A$, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are $349{\mu}g$/${\sqrt}$Hz, $341{\mu}g$/${\sqrt}$Hz and $411{\mu}g$/${\sqrt}$Hz, respectively.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.559-560
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• 2008

In this paper, I proposed 10bits 40MS/s Pipelined A/D converter. The op-amps for SHA and MDAC designed folded-cascode amplifier with gain-booster. And the MOS transistors with a low threshold voltage are employed to low on-resistor and parasitic capacitance. The power dissipation is 119㎽ at 1.2V and 40MS/s

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.236-241
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• 2017

This paper presents a single-phase grid connected voltage-ed inverter with a power decoupling circuit. In the single-phase grid connected voltage-ed inverter, it is well known that a power pulsation with twice the grid frequency is contained in the input power. In a conventional voltage type inverter, electrolytic capacitors with large capacitance have been used in order to smooth the DC voltage. However, lifetime of those capacitors is shortened by the power pulsation with twice grid frequency. The authors have been studied a active power decoupling(APD) method that reduce the pulsating power on the input DC bus line, this enables to transfer the ripple energy appeared on the input DC capacitors into the energy in a small film capacitor on the additional circuit. Hence, extension of the lifetime of the inverter can be expected because the small film capacitor substitutes for the large electrolytic capacitors. Finally, simulation and experimental results are discussed.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.1
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• pp.29-34
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• 2015

DC bus electrolytic capacitors are used in variety of equipments as smoothing element of the power converters because it has high capacitance for its size and low price. It is responsible for frequent breakdowns of many static converters and inverter drive systems. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure of power converter. In this paper, the on-line remote diagnosis monitoring system for DC BUS electrolytic capacitors of power converter using low-cost type Zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using AC coupling method of DC link ripple voltage/current. The Zigbee communication-based experimental results show that the proposed remote DC capacitor diagnosis monitoring system can be applied to DC/DC converter and UPS successfully.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.262-266
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• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.497-507
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• 2010

This paper presents current unbalance improved half-bridge LLC resonant converter using the two transformers with different leakage inductances. The proposed converter resonates with the leakage inductance and magnetizing inductance of the transformer and the resonant capacitance. The converter operates in a wide load range and satisfies the zero voltage switching even under the light load. The series-parallel connected two transformers act as the transformers or the resonant inductances according to the operational modes, and the separate output filter inductance in the transformer secondary is not needed using the leakage inductance. The current unbalance of the secondary diode rectifier is improved using the different leakage inductances of the two transformers and the asymmetrical pulse-width modulation (PWM). In this paper, the operational principle of the converter is explained by the modes, and the design example for the prototype is also shown. To validate the performance of the converter, the prototype is implemented as the designed circuit parameters and the good performance of the proposed converter is shown through the experimental results

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.