• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.276-277
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• 2017

전력변환장치에 널리 사용되는 전해 캐패시터는 그 수명이 상대적으로 짧은 것으로 알려져 있으며, 전력변환장치의 신뢰성 확보를 위해서는 등가직렬저항 또는 캐패시턴스의 추정을 통해 전해 캐패시터의 열화상태를 진단할 필요가 있다. 본 논문에서는 부스트 컨버터에서 평균 모델 기반 디지털 제어를 통해 전해 캐패시터의 캐패시턴스를 추정하는 방법에 대해 연구를 진행하였고, 시뮬레이션과 실험을 통해 그 특성을 평가하였다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.395-396
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• 2015

본 논문에서는 수퍼커패시터 에너지 저장장치의 DC링크 커패시터뱅크 커패시턴스 추정에 관하여 기술한다. DC링크 커패시터뱅크에 임의의 주파수성분의 전류를 주입하여 생성되는 전압과 전류의 AC성분의 관계로 커패시턴스를 추정하였다. 제안한 방법은 온라인으로 실시간 추정이 가능하며, BPF(Band Pass Filter)를 구성하여 동일한 주파수 신호를 추출하여 커패시턴스를 추정한다. 100%, 110% 계통전압에서도 커패시턴스의 평균 값은 2.03F과 2F으로 나타났고, 분산은 0.0005와 0.0001로 나타나 동일한 추정 값이 연속해서 계산되어 타당성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.449-450
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• 2015

본 논문에서는 재귀최소자승법을 이용한 수퍼커패시터 뱅크의 실시간 커패시턴스 추정방법에 대해 서술하였으며, 커패시터의 수명은 초기용량에서 약 25%가 감소한 경우 수명을 다했다고 판단한다. 수명을 다한 커패시터를 사용할 경우 시스템의 성능과 안전을 보장할 수 없으므로 커패시터를 교체할 적절한 시기를 판단하는 것은 매우 중요하다. 따라서 본 논문에서는 재귀최소자승법으로 수퍼커패시터 뱅크의 커패시턴스를 측정할 수 있는 방법을 제안하였고, 이를 시뮬레이션을 통해 타당성을 검증하였다.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.372-376
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• 2010

Electrolytic capacitors have been widely used in power electronics system because of the features of large capacitance, small size, high-voltage, and low-cost. Electrolytic capacitors, which is most of the time affected by aging effect, plays a very important role for the power electronics system quality and reliability. Therefore it is important to estimate the parameter of an electrolytic capacitor to predict the failure. The estimation of the equivalent series resistance(ESR) is important parameter in life condition monitoring of electrolytic capacitor. This paper proposes a simple technique to measure the ESR of an electrolytic capacitor. This method uses a switching DC/DC boost converter to measure the DC Bus capacitor ESR of power converter. Main advantage of the proposed method is very simple in technique, consumes very little time and requires only simple instruments. Simulation results are shown to verify the performance of the proposed method.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.177-178
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• 2015

본 논문에서는 수퍼커패시터 뱅크로 구성된 에너지 저장장치의 DC링크에 임의의 주파수성분의 AC전압과 전류를 통해 측정된 임피던스의 크기와 위상차를 통하여 실시간으로 커패시턴스를 추정하는 방법에 대한 검증 결과를 기술하고, 수퍼커패시터의 용량 및 계통의 변화에 따라 측정값의 결과를 비교 분석 하였다. 수퍼커패시터 뱅크는 정상 계통인 경우 평균 1.95F 으로 정격용량의 약 85%가 추정 되고 계통의 크기를 90%, 110%로 변화함에 있어서도 동일한 결과를 얻었다. 수퍼커패시터 뱅크의 커패시턴스에 변화를 주었을 경우에도 최대 오차율 약 1.5% 이내에 반복적으로 추정되는 것을 확인하여 수퍼커패시터 뱅크의 커패시턴스 추정방법이 타당함을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.47-54
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• 2004

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1458-1467
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• 1999

VLSI 공정 기술이 발달하면서 이웃한 전선 간의 간격이 점점 더 가까워 지고 있으며, 그에 따라 인접 전선 간의 혼신 문제가 심각해지고 있다. 본 논문에서는 3층 그리드 채널 배선에 적용 가능한 혼신을 최소화시키는 배선층 할당 방법을 제안한다. 이 방법은 선형 의사 불린 최적화 기법에 맞도록 고안되었으며, 적절한 변수 선택 휴리스틱과 상한값 추정 방법을 통하여 최적의 결과를 짧은 시간 안에 찾아낸다. 실험 결과를 통하여, 일반적인 0/1 정수 선형 프로그래밍 기법과 비교하여 성능과 수행시간 면에서 우수함을 보인다. Abstract Current deep-submicron VLSI technology appears to cause crosstalk problem severe since it requires adjacent wires to be placed closer and closer. In this paper, we deal with a horizontal layer assignment problem for three layer HVH channel routing to minimize coupling capacitance, a main source of crosstalk. It is formulated in a 0/1 integer linear programming problem which is then solved by a linear pseudo boolean optimization technique. Experiments show that accurate upper bound estimation technique effectively reduces crosstalk in a reasonable amount of running times.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.117-122
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• 2018

A large-capacity three-phase system air conditioner recently includes an inverter circuit to reduce power consumption. The inverter circuit uses a DC voltage that comes from DC-link power capacitor with the function of rectifying, which means AC voltage to DC voltage using a diode. An electrolytic capacitor is generally used to satisfy the voltage ripple and current ripple conditions of a DC-link power capacitor used for rectifying. Reducing the capacitance of the capacitor decreases the size, weight, and cost of the circuit. This paper proposes an algorithm to reduce the input ripple current by combining the minimum point estimation phase locked loop (PLL) phase control and the average voltage d axis current control technique. When this algorithm was used, the input ripple current decreased by almost 90%. The current ripple of the DC-link capacitor decreased due to the decrease in input ripple current. The capacitor capacity can be reduced but the electrolytic capacitor has a heat generation problem and life-time limitations because of its large equivalent series resistance (ESR). This paper proposes a method to select a film capacitor considering the current ripple at DC-link stage instead of an electrolytic capacitor. The capacitance was selected considering the voltage limitation, RMS (Root Mean Square) current capacity, and RMS current frequency analysis. A $1680{\mu}F$ electrolytic capacitor can be reduced to a $20{\mu}F$ film capacitor, which has the benefit of size, weight and cost. These results were verified by motor operation.

• Journal of Hydrogen and New Energy
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• v.20 no.1
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• pp.38-44
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• 2009

Recently, the research focused on fuel cell hybrid vehicles (FCHVs) is becoming an attractive solution due to environmental pollution generated by fossil fuel vehicles. The proper energy control strategy will result in extending the fuel cell lifetime, increasing of energy efficiency and an improvement of vehicle performance. Battery state of charge (SoC) is an important quantity and the estimation of the SoC is also the basis of the energy control strategy for hybrid electric vehicles. Estimating the battery's SoC is complicated by the fact that the SoC depends on many factors such as temperature, battery capacitance and internal resistance. In this paper, battery charging time estimated by SoC is studied by using the speed response and current response. Hybrid system is consist of a fuel cell unit and a battery in series connection. For experiment, speed response of vehicle and current response of battery were determined under different state of charge. As the results, the optimal battery charging time can be estimated. Current response time was faster than RPM response time at low speed and vice versa at high speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.1-10
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• 2003

Device characteristics of the Metal-Ferroclecric-Semiconductor FET(MFSFET) are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V$_{G}$ curves generated from our MFSFET simulation exhibit the accumulation, the depletion and the inversion regions clearly. The capacitance, the subthreshold and the drain current characteristics as a function of gate bias exhibit the memory windows are 1 and 2 V, when the coercive voltages of ferroelectric are 0.5 and 1 V respectively. I$_{D}$-V$_{D}$ curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I$_{D}$-V$_{D}$ curve is 1.5, 2.7, 4.0, and 5.7 ㎃, when the gate biases are 0, 0.1, 0.2 and 0.3V respectively. As the drain current is demonstrated after time delay, PLZT(10/30/70) thin film shows excellent reliability as well as the decrease of saturation current is about 18 % after 10 years. Our simulation model is expected to be very useful in the estimation of the behaviour of MFSFET devices.T devices.