• Aerospace Engineering and Technology
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• v.4 no.1
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• pp.86-94
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• 2005

This paper shows the results of design, analysis, manufacturing and test performed to develop the CTU(Command Telemetry Unit) EQM(Engineering Qualification Model). According to the key requirement specifications, the logics and circuits of each board are designed. In order to validate designs, some worst case, part stress, reliability, FMECA, radiation environment and launch environment analyses are performed. After manufacturing and assembling all boards, all functions of CTU EQM are verified through the functional test, environmental test and ETB test.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.9
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• pp.114-121
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• 2004

Thermal design changes and analysis on the engineering model of Command Telemetry Unit(CTU) for a geostationary communications satellite arc performed for the purpose of developing an engineering qualification model. A thermal model is developed by using power consumption measurement values of each functional board and thermal cycling test results. In modeling heat dissipated EEE parts, heat dissipation is imposed evenly on the EEE part footprint area which is projected to the printed circuit board. All the EEE parts of CTU meet the requirement of their allowable temperature range when placed on the engineering qualification level of thermal vacuum environments in accordance with the proposed thermal design changes.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.4
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• pp.100-109
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• 2005

This paper introduce electromagnetic environmental requirements, test procedures and test results for the Command Telemetry Unit(CTU), which is engineering qualification model for communication satellite in geostationary earth orbit. Also, through debugging of the CTU during the Electro Magnetic Compatibility(EMC) tests, this paper evaluates characteristics of noise generated by the CTU. It is also obtained that better EMC performance can be acquired by improving electrical power converter module of the CTU.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.7
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• pp.98-105
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• 2005

In this paper, the decryption function of CCSDS telecommand of CTU EQM for the security of communications satellite was verified. In order to intensify the security level of DES CFB decryption algorithm applied to CTU EM, 3DES CFB decryption algorithm using three keys is implemented in the CTU EQM. As the decryption keys increased due to the 3DES algorithm, the keys and IV are stored in PROM memory, and used for the telecommand decryption by taking the keys and IVs corresponding to the selected key and IV indexes from the memory. The operation of the 3DES CFB is validated through the timing simulation of 3DES CFB algorithm, and then the 3DES CFB core implemented on the A54SX32 FPGA. The test environment for the telecommand decryption verification of the CTU EQM was built up. Through sending and decrypting the encrypted command, monitoring the opcodes, and confirming LED on/off by executing the opcodes, the 3DES CFB telecommand decryption function of the CTU EQM is verified.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.3
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• pp.95-100
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• 2003

Electronic equipment used in satellites are demanding extremely high reliability, so they should be designed to have immunity for some critical faults by using redundancy component. Generally, Communication satellites are assigned to meet the 15 years mission lifetime, of the analysis about faults must be performed to electronic equipments of satellite. This paper is a summary of the fault tolerance design research of command processor, the improvement of reliability and trade-off study of fault tolerance design result. The reliability prediction value of the satellite component used in this research was taken from Koreasat 3 and Kompsat 1. It is important to perform many trade-off studies for fault tolerance design, especially to choose the most proper fault tolerance method for the specified fault scenario.

• Bulletin of the Korean Space Science Society
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• 2004.10b
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• pp.270-273
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• 2004

The initial thermal analysis needs to be fast and efficient to reduce the feedback time for the optimal electronic equipment designing. In this study, a thermal model is developed by using power consumption measurement values of each functional breadboard, that is, semi-empirical power dissipation method. In modeling heat dissipated EEE parts, power dissipation is imposed evenly on the EEE part footprint area which is projected to the printed circuit board, and is called surface heat model. The application of these methods is performed in the development of a command and telemetry unit (CTU) for a geostationary satellite. Finally, the thermal cycling test is performed to verify the applied thermal analysis methods.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.29 no.4 s.235
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• pp.526-536
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• 2005

A heat dissipation modeling method of EEE parts, or semi-empirical heat dissipation method, is developed for thermal design and analysis an electronic equipment of geostationary satellite. The power consumption measurement value of each functional breadboard is used for the heat dissipation modeling method. For the purpose of conduction heat transfer modeling of EEE parts, surface heat model using very thin ignorable thermal plates is developed instead of conventional lumped capacity nodes. The thermal plates are projected to the printed circuit board and can be modeled and modified easily by numerically preprocessing programs according to design changes. These modeling methods are applied to the thermal design and analysis of CTU (Command and Telemetry Unit) and verified by thermal cycling and vacuum tests.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.170-176
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• 2004

In this study, the relay driver circuit which controls the spacecraft configuration change are implemented and validated. First of all, the specification of the relay driver circuit is defined, and then its circuit meeting the specification defined is designed. In order to verify the design of the relay driver circuit, its circuit was simulated, and then it's confirmed that the relay pulse current and voltage level defined in the specification are obtained, and the results obtained through the functional test of the relay driver circuit are compared and well matched with the simulation results. Also the worst case analysis for confirming the stable operation of the relay driver circuit under the tolerance of each component is performed.