• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.