• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2401-2409
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• 2016

Android CPU governors exploit the DVFS (Dynamic Voltage Frequency Scaling) technique. The DVFS is a power management technique where the CPU operating frequency is decreased to allow a corresponding reduction in the CPU supply voltage. The power consumed by a CPU is approximately proportional to the square of the CPU supply voltage. Therefore, lower CPU operating frequency allows the CPU supply voltage to be lowered. This helps to reduce the CPU power consumption. However, lower CPU operating frequency increases a task's execution time. Such an increase in the task's execution time makes the task's response time longer and makes the task's deadline miss occur. This finally leads to degrading the quality of service provided by the task. In this paper, we evaluated the performance of Android CPU governors in terms of the power consumption, tasks's response time and deadline miss ratio.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2213-2221
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• 2015

The ondemand governor used in android-based smartphone platforms is a CPU frequency scaling technique. The ondemand governor sets the CPU operating frequency depending on the CPU utilization rate. Job scheduling affects the CPU utilization rate. The power consumption is proportional to the value of operating frequency. Consequently, CPU frequency scaling and CPU utilization rate have an effect on power consumption in a smartphone. In this paper, we evaluated the performance of job scheduling techniques incorporating the ondemand governor in terms of CPU utilization, power consumption, and job deadline miss ratio.

• Journal of Korea Game Society
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• v.17 no.4
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• pp.137-148
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• 2017

Since the power consumption of data centers is large and computer serves take a large portion of it, there have been much research on the power saving of servers in various ways recently. Among the units of severs CPU is one of major power consuming units. In this paper, a method of client-server assignment for minimizing the CPU power consumption of servers in a game server cluster is proposed. We model the client-server assignment problem as an optimization problem, and find a solution to the problem using a simulated annealing-based technique. One of major features of our method is to select a proper operating frequency according to the amount of load on a server. The selection of a lower frequency in case of low load will result in reducing power consumption. To our survey, little research on client-server assignment in consideration of power consumption has been carried out.

• Journal of Computing Science and Engineering
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• v.6 no.2
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• pp.79-88
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• 2012

Power continues to be a driving force in central processing units (CPU) design. Most of the advanced breakthroughs in power have been in a realm that is applicable to workstation CPUs. Advanced power management systems will manage temperature, dynamic voltage scaling and dynamic frequency scaling in a CPU. The use of power management systems for microcontrollers and embedded CPUs has been modest, and mostly focuses on very large scale integration (VLSI) level optimizations compared to system level optimizations. In this paper, a dynamic frequency controlling (DFC) technique is introduced, to lay the foundation of a system level power management system for commercial microcontrollers. The DFC technique allows a commercial microcontroller to have minor modifications on both the hardware and software side, to allow the clock frequency to change to save power; results in this study show a 10% savings. By adding an additional layer of software abstraction at the interrupt level, the microcontroller can operate without having knowledge of the current clock frequency, and this can be accomplished without having to use an embedded operating system.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.12
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• pp.541-554
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• 1986

This paper presents the results of driving performance analysis of permanent magnet synchronous motor using a microprocessor based control system. The system consists of three phase power transistor inverters, three phase controlled rectifier, three central processing units, and sensors. The three CPUs are, respectively, used to generate PWM control signals for the inverter generating three phase sine wave, to generate the gate control signals for firing the converter, and to supervise other two CPUs. The supervisor is used to compute PI control algtorithm to three phase reference sine wave for the inverter. It is also used to maintain a constant voltage frequency ratio for the converter operating as a constant torque controller. The inverter CPU retrieves precomputed PWM patterns from look up tables because of computation speed limitations found in almost available microprocessors. The converter CPU also retrieves precomputed gate control patterns from another look-up tables. For protecting the control ststem from any damage by extraordinary over currents, the supervisor receives the data from current sensor, CT, and break down the CB to isolate the circuits from source. A resolver has a good performance characteristics of overall speed range, especially on low speed range. Therefor the speed control accuracy is impoved. The microprocessor based PM synchronous motor control system, thus, has many advantages such as constant torque characteristics, improvement of wave, limitation on extraordinary over currents, improvement of speed control accuracy, and fast response speed control using multi-CPU and look-up tables.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1165-1168
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• 1998

This paper describes a 72-word by 32-bit 2-read/1-write multi-port register file, which is suitable for 32-bit RISC/DSP microprocessors. To minimize area and achieve high speed, advanced single-ended sense amplifiers are used. Each part of circuit is optimized at transistor level. The verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, it was laid out in a 0.6um 1-poly 3-metal layer CMOS technology. The simulation results show maximum operating frequency is 179MHz in worst case conditions. It contains 27,326 transistors and the size is 3.02mm by 2.20mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.388-397
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• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.