• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.185-197
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• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.

• Journal of Advanced Navigation Technology
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• v.27 no.3
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• pp.306-313
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• 2023

Realistic and graphics-based virtual reality content is based on 360-degree videos, and viewport extraction through the viewer's intention or automatic recommendation function is essential. This paper designs a viewport extraction system based on multiple object tracking in 360-degree videos and proposes a parallel computing structure necessary for multiple viewport extraction. The viewport extraction process in 360-degree videos is parallelized by composing pixel-wise threads, through 3D spherical surface coordinate transformation from ERP coordinates and 2D coordinate transformation of 3D spherical surface coordinates within the viewport. The proposed structure evaluated the computation time for up to 30 viewport extraction processes in aerial 360-degree video sequences and confirmed up to 5240 times acceleration compared to the CPU-based computation time proportional to the number of viewports. When using high-speed I/O or memory buffers that can reduce ERP frame I/O time, viewport extraction time can be further accelerated by 7.82 times. The proposed parallelized viewport extraction structure can be applied to simultaneous multi-access services for 360-degree videos or virtual reality contents and video summarization services for individual users.

• Journal of Korea Multimedia Society
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• v.8 no.3
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• pp.355-361
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• 2005

This paper proposed a system collecting image information by agents in multi-threaded environment and then retrieving them with content based image retrieval. This system uses multi threads to retrieve web information effectively, then improves efficiency of CPU cycles to reduce latency time, which is the time requesting queries, executing communication processing 4hat the retrieval agents perform and filtering the retrieval results. Also, the agents for image retrieval use Java language, which is platform independent, to be suitable for distributed environment. Using JDBC to save the retrieved images, the agents are connected to database. The images themselves are stored in distributed agents' databases, and only the image indexes are stored in an index server so that the efficiency of storage and retrieval time can be improved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.6
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• pp.761-767
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• 1998

The Perfectly Matched Layer(PML) provide good performance in absorption over a wide frequency range and is an appropriate ABC for waveguides with high dispersion. In this paper, a novel algorithm is proposed to improve the computational efficiency of the PML. In the input and output ports, the fields are decomposed into a series of modes, and then an appropriate ABC is applied to each mode. CPU time and memory storage requirements are greatly reduced, since the computational region is analyzed in one dimension. A WG-90 rectangular waveguide with a thick asymmetric iris is analyzed by Finite-Difference Time-Domain(FDTD) simulations with the conventional PML and the proposed one-dimensional (1-D) PML. Numerical results show that the computational efficiency is significantly improved by the proposed method.

• Journal of KIISE:Software and Applications
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• v.34 no.3
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• pp.246-254
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• 2007

Local search algorithms start from a certain candidate solution and probe its neighborhood to find ones with improved quality. This paper proposes a method of probabilistically filtering out bad-looking neighbors based on a simple low-cost preliminary evaluation heuristics. The probabilistic filtering enables us to save time wasted on fully evaluating those solutions that will eventually be trashed, and thus improves the search efficiency by allowing us to spend more time on examining better looking solutions. Experiments with two large-scaled real-world problems, which are a traffic signal control problem in traffic network and a load balancing problem in production scheduling, have shown that the proposed method finds better quality solutions, given the same amount of CPU time.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06c
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• pp.1-4
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• 2011

악취 유발 사업장 및 지자체에서 사용하고 있는 악취 관리 모델링 시스템의 핵심 모듈을 최근 Intel에서 발표한 멀티코어(multi-core) 기술과 OpenMP 기술을 이용하여 고성능 병렬처리에 의한 실시간 시스템으로 개선하였다. 기존의 기상 모델인 CALMET 모델과 대기질 모델인 CALPUFF 모델은 배출원 갯수와 모델링 영역의 격자 갯수 증가에 따라 모델링 수행 시간이 기하급수적으로 증가한다. 악취는 그 특성상 모델링 수행시간을 짧게 할수록 악취모델링 결과를 효과적으로 사용할 수 있다. 따라서 모델링 수행시간을 단축하기 위해 여러 개의 CPU Core를 동시에 사용하여 병렬로 작업을 처리하는 멀티코어 기술을 접목하여, 기존의 CALPUFF를 실시간 모델링이 가능한 고성능 모델링 시스템으로 개발하였다. 실험 결과 Core의 수가 증가하면 Amdahl의 법칙에 준하여 가속화되었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9C
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• pp.859-868
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• 2006

H.264에서 다중참조 프레임을 사용한 움직임 예측 방법은 단일 참조프레임을 이용한 움직임 예측보다 더 많은 시간적 중복성을 제거하여 부호화 효율을 높이거나 채널에러에 강인하게 부호화하기 위해 사용된다. 하지만 다중 참조 프레임을 이용하여 움직임 예측을 하는 것은 단일의 참조 프레임을 이용하는 것보다 많은 계산량을 요구하기 때문에 비디오 인코더의 복잡도를 증가시키게 된다. 본 논문에서는 다중참조 프레임을 사용한 움직임 예측을 화질 열화 없이 적은 복잡도로서 가능하게 하는 알고리즘을 제안한다. 움직임 예측 절차의 복잡도를 줄이기 위해, 제안한 알고리즘에서는 연속되는 프레임 사이에 구성된 움직임 벡터맵을 이용하여 움직임벡터를 추정한다. 제안한 방식은 추정된 움직임벡터를 작은 탐색영역에서 보정하는 방식을 적용하기 때문에 기존의 방식들에 비해 적은 복잡도가 요구된다. 제안된 방법으로 추정된 움직임벡터는 각 참조프레임들에 대해 최적의 움직임 벡터를 효과적으로 추적하기 때문에 부호화 된 영상의 화질은 전 탐색영역 움직임 예측 알고리즘을 이용한 결과와 매우 비슷하다. 제안된 방식은 세가지 단계로 구성된다. (a) 연속되는 두 개의 프레임 사이에 벡터맵을 구성한다. (b) 벡터맵에 있는 요소벡터를 이용하여 시간적 움직임 벡터를 구성한다. (c) 마지막으로, 임시 움직임 벡터를 좁은 탐색영역에서 보정한다. 컴퓨터 실험을 통해 제안된 방식의 효율성을 입증하였다. 제안된 방식과 기존의 방식들과의 비교를 위해 H.264 부호화기에서 움직임 예측 모듈에 의해 소비된 CPU 시간을 측정하였다. 컴퓨터 실험을 통해 알 수 있듯이 제안된 방식에 의해 부호화된 영상의 화질은 기존 방식과 을 통해 얻은 영상화질과 거의 같으면서 알고리즘 복잡도는 크게 줄어드는 것을 볼 수 있다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.45-46
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• 2018

본 논문에서는 시간에 엄격한(Time critical) 산업용 IoT(Industrial IoT) 환경의 무선 센서 네트워크 시스템 상의 효율적인 패킷 전달과 정확도(Accuracy) 향상을 위해 강화학습과 EDF 알고리즘을 혼합한 스케쥴링 기법을 제안한다. 이 방식은 다중 대기열(Multiple queue) 환경에서 각 대기열의 요구 정확도(Accuracy Requirement)를 기준으로 최대한 패킷 처리를 미룸으로써 효율적인 CPU자원 분배와 패킷 손실율(Packet Loss)을 조절한다. 제안하는 기법은 무선 센서 네트워크 상의 가변적이고 예측 불가능한 환경에 대한 사전지식이 없이도 요구하는 서비스의 질(Quality of service)를 만족할 수 있도록 한다. 또한 정확도를 요구조건으로 제시하여 마감시간이 중요시되는 작업에서도 효율을 최대화한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1297-1304
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• 2000

The full wave method requires a great number of computer memory and lasting long CPU time for the calculation of the discontinuity problems in microstrip structures. While the computation only for the transverse field components at those structures causes the both of time and memory reduction. For the case of the calculating only transverse components for the most of microstrip structures such as low-pass filter, branch coupler and patch antenna the computer memory and running time can be reduced to about 50% and 33%, comparing to the full wave computation. Consequently, the proposed method than that of TEM-mode has an advantages of higher speed and less memory than that of conventional FDTD analysis.