• 한국윤활학회:학술대회논문집
• /
• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
• /
• pp.435-437
• /
• 2002

Polishing of copper, a process called copper chemical mechanical polishing, is a critical, intermediate step in the planarization of silicon wafers. During polishing, the electrodeposited copper films are removed by slurries: and the differential polishing rates between copper and the surrounding silicon dioxide leads to a greater removal of the copper. The differential polishing develops dimples and furrows; and the process is called dishing and erosion. In this work, we present the results of experiments on dishing and erosion of copper-CMP, using patterned silicon wafers. Results are analyzed for the pattern factors and properties of the copper layers. Three types of pads - plain, perforated, and grooved - were used for polishing. The effect of slurry chemistries and pad soaking is also reported.

• 품질경영학회지
• /
• 제45권2호
• /
• pp.293-306
• /
• 2017

Purpose: In this study, an optimal design level of influencing factors on semiconductor polishing process was determined to minimize flexion of both sides on wafers. Methods: First, significant interactions are determined by the stepwise regression method. ANOVA analysis on SN ratio and mean of dependent variable are performed to draw mean adjustment factors. In addition, the optimal levels of mean adjustment factors are decided by comparing means of each level of mean adjustment factors. Results: As a result of ANOVA, a mean adjustment factor was determined as a width of formed flexion on the plate. The mean of the difference has the nearest to 0 in the case when the width of formed flexion has level 2 (4mm). Conclusion: Optimal design levels of semiconductor polishing process are determined as follows; (i) load applied to the wafer carrier has a level 1 (3psi), (ii) load applied to the wafer has a level 1(3psi), (iii) the amount of slurry supplied during polishing has a level 3 (300 co/min), (iv) the width of formed flexion on the plate has level 2 (4mm).

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.136-139
• /
• 2004

The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.

• 한국세라믹학회지
• /
• 제40권1호
• /
• pp.77-80
• /
• 2003

수용액 내에서 질화물 박막의 산화저항성 흡착 피막의 형성을 확인하기 위하여 Si$_3$N$_4$분말 표면의 glycine 흡착 거동을 조사하였다. 염기성분위기에서 glycine은 Si$_3$N$_4$ 분말 표면에 포화 흡착되었으며 이러한 흡착거동은 Si$_3$N$_4$ 박막의 경우에도 동일하게 일어날 것으로 예상되었다. Glycine을 첨가한 CeO$_2$ 슬러리를 제조하고 PH에 따른 Si$_3$N$_4$와 SiO$_2$ 박막의 연마시험을 수행하여 연마율은 감소하고 선택비는 증가하는 것을 확인하였다. 실험에서 얻은 최대 선택비는 pH=12에서 35 이상이었다. 이는 염기성 분위기에서 glycine이 해리하여 막 표면에 화학흡착하고 산화와 용해를 억제함으로써 연마율을 낮추고 선택비 향상에 기여하였기 때문으로 판단된다. 아미노산 계열의 첨가제를 CeO$_2$계 CMP용 슬러리에 적용하는 경우 산화물/질화물 박막의 선택비를 향상시키는데 효과적임을 확인하였다.