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http://dx.doi.org/10.7469/JKSQM.2017.45.2.293

Determination of Optimal Design Level for the Semiconductor Polishing Process by Taguchi Method  

Sim, Hyun Su (Department of Industrial and Management Engineering, Kyonggi University Graduate School)
Kim, Yong Soo (Department of Industrial and Management Engineering, Kyonggi University)
Publication Information
Journal of Korean Society for Quality Management / v.45, no.2, 2017 , pp. 293-306 More about this Journal
Abstract
Purpose: In this study, an optimal design level of influencing factors on semiconductor polishing process was determined to minimize flexion of both sides on wafers. Methods: First, significant interactions are determined by the stepwise regression method. ANOVA analysis on SN ratio and mean of dependent variable are performed to draw mean adjustment factors. In addition, the optimal levels of mean adjustment factors are decided by comparing means of each level of mean adjustment factors. Results: As a result of ANOVA, a mean adjustment factor was determined as a width of formed flexion on the plate. The mean of the difference has the nearest to 0 in the case when the width of formed flexion has level 2 (4mm). Conclusion: Optimal design levels of semiconductor polishing process are determined as follows; (i) load applied to the wafer carrier has a level 1 (3psi), (ii) load applied to the wafer has a level 1(3psi), (iii) the amount of slurry supplied during polishing has a level 3 (300 co/min), (iv) the width of formed flexion on the plate has level 2 (4mm).
Keywords
CMP(Chemical Mechanical Planarization); Taguchi Method; SN(Signal to Noise) Ratio; Robust Design;
Citations & Related Records
Times Cited By KSCI : 10  (Citation Analysis)
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