• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.526-529
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67ns access time for a 3-V powr supply. It was achieved using the sense amplifier with multiple point sensing scheme and high speed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5.mu.m double-polysilicon and triplemetal CMOS process technology. A die size is 1.78mm*2.13mm.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.63-66
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• 2000

In this paper, we propose two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistor 1 and 2 employ a P-type folded composite transistor and an electronic zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried oui using 0.25$\mu\textrm{m}$ n-well process with 2.5V supply voltage.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.212-221
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• 1996

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.300-305
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.

• The Magazine of the IEIE
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• v.13 no.1
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• pp.86-95
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• 1986

The basic physical principles involved in the operation of monolithic magnetic sensors are reviewed and technological aspects outlined. More or less conventional devices based on Hall effect, magnetoresistance or current path deflection are described. It is shown that such sensors with 2, 3, 4 or 5 terminal contacts are achievable with standard silicon integrated circuit process. Several kinds of magnetodiodes (p+nn+,p+n, Schottky, MOS, memory, CMOS) have been fabricated on Si and on SOS films and present attractive properties. Finally, the magneto-transistor family is discussed with emphasis to split-terminals, CMOS, unijunction and fila-mentary devices.

• Review of KIISC
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• v.2 no.2
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• pp.64-80
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• 1992

전화망을 통과하는 음성신호에 대하여, 실시간에 공개열쇠방식의 암호화/복호화를 하기 위한 반도체 IC제조공정평가를 실시하였다. 초당 64k bit의 정보에 대하여 256 bit이상의 key를 갖는 RSA 방식 암호화를 위하여 modular multiplication 환경과 redundant number system을 채택하여 algori-multiple input shift register 를 사용하는 회로로 충족시키는 과정에서, 1.0 $이하의 CMOS공정이 요구된다는 결론에 도달하였으며, 이들 회로의 타당성은 저속 RSA chip의 분석 결과와 비교하여 확인하였다.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.343-346
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• 2004

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.