• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.278-281
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• 2014

This paper presents the performance comparison of three types of full-wave rectifiers for vibration energy harvesting. The first rectifier is consisted of two active diodes and two MOSFETs, and the comparators of the active diodes are powered from the output of the rectifier. The second one is a 2-stage full-wave rectifier. It comprises the basic rectifier consisted of four MOSFETs and an active diode. The comparator is also powered from the output of the rectifier. The third one is an input powered rectifier. It has the same structure as the second rectifier, but the comparator is powered from the input of the rectifier. These rectifiers have been designed using a 0.35um CMOS process and their performances have been compared through simulations. In terms of efficiency, the first rectifier shows the best performance at heavy loads, but the second one is suitable at light loads. When the power consumption during absence of vibration is more important than efficiency, the input-powered rectifier is proper.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.585-588
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• 2014

This paper presents a self-powered sensor node circuit using photovoltaic and vibration energy harvesting. The harvested energy from a solar cell and a vibration device(PZT) is stored in a storage capacitor. The stored energy is managed by a PMU(Power Management Unit). In order to supply a stable voltage to the sensor node, an LDO(Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter), and 10-bit digital output data corresponding to current temperature is obtained. The proposed circuit is designed in a 0.35um CMOS process, and the designed chip size including PADs is $1.1mm{\times}0.95mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.577-580
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• 2014

In this paper an auto-switching dual-input energy harvesting circuit is proposed. Since the maximum power points of a thermoelectric generator(TEG) output and a vibration device(PEG) output is 1/2 of their open-circuit voltage, an identical MPPT controller can be used for both energy sources. The proposed circuit monitors the outputs of the TEG and PEG, and chooses the energy source generating a higher output using an auto-switching controller, and then harvests the maximum power from the selected device using a MPPT controller. The harvested energy is boosted through a charge pump and stored in a storage capacitor. The stored energy is provided to a load through a PMU(Power Management Unit). The proposed circuit is designed in a $0.35{\mu}m$ CMOS process and its functionality has been verified through extensive simulations. The designed chip occupies $1.4mm{\times}1.2mm$ including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.533-536
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• 2016

This paper describes a vibrational energy harvesting circuit with MPPT control. A high-performance AC-DC converter of which the efficiency is improved by using body-bias technique and bulk-driven technique is proposed and applied for the vibrational energy harvesting circuit design. MPPT (Maximum Power Point Tracking) control function is implemented using the linear relationship between the open-circuit voltage of a vibrational device and its MPP voltage. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a vibrational device, makes the reference voltages using sampled voltage and delivers the maximum available power to load. The proposed circuit is designed with a $0.35{\mu}m$ CMOS process, and the chip area is $1.21mm{\times}0.98mm$.

• Journal of IKEEE
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• v.23 no.3
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• pp.954-961
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• 2019

This paper suggests an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The memory cell consists of symmetric 8 transistors, in which the latch storing data is controlled by a column-wise assistline. During the read, the data storage nodes are temporarily decoupled from the read path, thus eliminating the read disturbance. Additionally, the cell keeps the noise-vulnerable 'low' node close to the ground, thereby improving the dummy-read stability. In the write, the boosted wordline facilitates to change the contents of the memory bit. At 0.4 V supply, the advanced 8T cell achieves 65% higher dummy-read stability and 3.7 times better write-ability compared to the commercialized 8T cell. The proposed cell and circuit techniques have been verified in a 16-kbit SRAM array designed with an industrial 180-nm low-power CMOS process.

• Journal of IKEEE
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• v.23 no.3
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• pp.947-953
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• 2019

The purpose of this paper is to explore an ASIC design for estimating sizes and concentrations of airborne micro-particles by the means of integrating, amplifying and digitizing electric charge signals generated by photo-sensors as it receives scattered photons by the presence of micro-particles, consisting of a pre-amplifier that detects and amplifies voltage or current signal from photo-sensor that generates charges (hole-electron pairs) when exposed to visible rays, infrared rays, ultraviolet rays, etc. according to the intensity of rays; a shaper for shaping the amplified signal to a semi-gaussian waveform; two discriminators and binary counters for outputting digital signals by comparing the magnitude of the shaped signal with an arbitrary reference voltages. The ASIC with the proposed architecture and functional blocks in this study was designed with a 0.18um standard CMOS technology from Global Foundries and the operation and performances of the ASIC has been verified by the silicons fabricated by using the process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.3
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• pp.311-317
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• 2019

We first numerically analyzed the characteristics of a silicon-based grating structure for beam steering. The analysis includes the basic principle of the grating structure according to the wavelength, peak radiation angle, radiation efficiency, and full-width at the half maximum(FWHM) of the radiation angle. Based on the analysis, we propose a silicon-based grating structure integrated with distributed Bragg reflector(DBR) to obtain a high radiation efficiency and narrow beam width simultaneously. We performed the numerical optimization of the radiation efficiency and FWHM of the radiation angle according to the DBR position. By the design optimization using the proposed grating structure compatible with the complementary metal-oxide semiconductor(CMOS) process, we achieved a maximum radiation efficiency of 87.1% and minimum FWHM of radiation angle of $4.68^{\circ}$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.