• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 2002년도 춘계공동학술대회
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• pp.301-305
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• 2002

Bioinformatics can beexplained as the science of developing algorithms, applicatiou tools, and computer databases and so on, for the purpose of supporting and enhancing biological research. Bioinformatic information systems (BIS) typically handle large data sets and the amount of the data goes up exponentially. Another impediment to easy extraction and retrieval of genomic data in BIS is the need to access different sites for similar information. Recently. there has been some attempts to integrate bioinformatics data in the World Wide Web (WWW) among the bioinformatics community by the internet computing technology. However, the work to integrate bioinformatics data on a universal platform has some problems because of the lack of standard, terminologies, semantics, and ontologies about bioinformatics. In this paper, an XML-based BIS architecture is proposed as an integrated BIS framework. The XML and related technologies allow the creation of meaningful information tags to exchange data between various databases as a standard format, and to create more simple interfaces. This integrated BIS framework has bioinformatic architectural components which is used in the Corporate Information Factory (CIF) method.

• 무역상무연구
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• 제35권
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• pp.3-38
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• 2007

As we know, D-terms which are constituted with DAF delivered the goods in a border place, DES delivered the goods on board a vessel at a vessel specified port on the buyer's side, DEQ delivered the goods on the quay on the buyer's side as the specified place, DDU and DDP delivered the good at the stipulated place at the agreed place or point, mean arrival contracts. DAF is designed mainly for railway carriage, DES and DEQ are designed mainly for vessel shipment, DDU and DDP are designed mainly for multimodal transportation. In spite of their original purpose of revision. They have in themselves many problems on notable points on application in practice. Therefore, in order to magnify their use, through revision of Incoterms, DAF is restricted to railway carriage, DES and DEQ are restricted to be used only for charter shipments. Particularly transport documents which seller should supply the buyer with under DDU and DDP are documents for ownership and possession rights to the goods loaded when executed in negotiable form like as CIF.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.2067-2070
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• 2002

In this paper, a VLSI architecture for transform and quantization module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• 한국응용곤충학회지
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• 제24권3호
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• pp.135-139
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• 1985

Influence of temperature, relative humidity, spore washing and spore drying on conidial germination of Alternaria porri(Ell.) Cif. was studied. Maximum conidial germination occurred at 100% relative humidity prevailing for 6 hours or more at $25^{\circ}C$. Conidial germination decreased with increase in number of spore washings. Drying of conidia for more than half an hour caused significant decrease in germination. In all the experiments, conidial germinatio increased with increase in incubation period.

• 전자통신동향분석
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• 제23권1호통권109호
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• pp.122-129
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• 2008

H.264의 출현으로 디지털 콘텐츠는 고해상도 HD 서비스로 빠르게 전환되고 있다. H.264는 현존하는 가장 우수한 비디오 부호화 표준이지만, 모바일 TV에서는 QVGA 또는 CIF 해상도의 VCD급 품질만 제공 가능한 성능의 한계를 보이고 있다. HD 콘텐츠에 익숙해진 사용자들은 모바일 TV의 VCD급 서비스에 점차적으로 불만족을 느끼게 될 것이며, DVD급 이상의 서비스로 빠른 전환을 요구하게 될 것이다. 본 고에서는 현재 모바일 TV에서 사용되는 H.264 보다 높은 압축 성능을 위한 비디오 부호화 표준화 동향과 전망에 대해 설명하고자 한다. 먼저 H.264 이후에 진행된 MPEG의 SVC, MVC, RVC 비디오 부호화 현황에 대해 설명하고, VCEG에서 진행중인 H.265를 위한 KTA 현황 및 동향과 주요 기술들에 대해 설명하고, 향후 비디오 부호화 표준화에 대한 전망을 예측하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.811-814
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• 2000

It this paper a VLSI architecture of the Shape-Adaptive Discrete Cosine Transform (SA-DCT) is described, which can be employed dedicatedly for MPEG-4 video codec. Adopting a fast DCT algorithm, the number of multipliers can be reduced by half in comparison with a conventional algorithm. This SA-DCT core with a small additional amount of hardware can perform the SA-Inverse DCT (SA-IDCT) by sharing multipliers and a transportation memory. The proposed SA-DCT core is integrated with 40,000 gates by using 0.35$mu$m triple-metal CMOS technology, which operates at 20 Mhz, and hence enables the realtime codec of CIF ($352{\times}288$ pixels) pictures.

• Journal of the Korean Data and Information Science Society
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• 제28권4호
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• pp.947-955
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• 2017

A competing risk analysis has been applied when subjects experience more than one type of end points. Geskus (2011) showed three types of estimators of CIF are equivalent under left truncated and right censored data. We extend his approach to an interval censored competing risk data by using a modified risk set and evaluate their performance under several sample sizes. These estimators show very similar results. We also suggest a test statistic combining Sun's test for interval censored data and Gray's test for right censored data. The test sizes and powers are compared under several cases. As a real data application, the suggested method is applied a data where the feasibility of the vaccine to HIV was assessed in the injecting drug uses.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.307-310
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• 2005

본 논문은 CMOS 센서의 ISP 전처리 과정 후 최종 화면에 출력하기 위한 효과적인 이미지 스케일 블록을 저전력, 저비용에 맞은 독립된 하드웨어 장치로 설계 하고자 한다. 카메라 센서 이미지 결과를 디스플레이 장치(OSD(On Screen Display)에 맞는 화면의 크기는 CIF(352${\times}$288), QCIF(176${\times}$144) 출력 모드를 사용한다. 최근 DMB 휴대용 멀티미디어 데이터 전송 사이즈 포맷에서도 위와 같은 사이즈를 지원하고 있다. 일반적인 스케일 처리에서는 PC 그래픽 카드(Graphic Card)장치의 지원을 받아서 처리하는 경우가 많다. 또는 CPU의 연산을 통한 CPU 자원을 점유하여 이미지 스케일을 처리하였다. 휴대용 CMOS 센서용에 적합한 독립적으로 처리할 수 있는 이미지 스케일 기능을 하드웨어로 설계하여 효과적인 시스템 운용과 고속 이미지 스케일 처리가 가능한 하드웨어를 설계하는게 목적이다. 이를 구현 하기위해 기존 알고리즘과 제안한 알고리즘을 비교하여 최적화된 알고리즘 적용하여 VHDL설계언어를 이용한 하드웨어 설계 후, ModelSim 6.0a를 이용하여 데이터를 검증한다.

• Communications for Statistical Applications and Methods
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• 제30권1호
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• pp.1-19
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• 2023

Observational data with missing or incomplete data are common in biomedical research. Multiple imputation is an effective approach to handle missing data with the ability to decrease bias while increasing statistical power and efficiency. In recent years propensity score (PS) matching has been increasingly used in observational studies to estimate treatment effect as it can reduce confounding due to measured baseline covariates. In this paper, we describe in detail approaches to competing risk analysis in the setting of incomplete observational data when using PS matching. First, we used multiple imputation to impute several missing variables simultaneously, then conducted propensity-score matching to match statin-exposed patients with those unexposed. Afterwards, we assessed the effect of statin exposure on the risk of heart failure-related hospitalizations or emergency visits by estimating both relative and absolute effects. Collectively, we provided a general methodological framework to assess treatment effect in incomplete observational data. In addition, we presented a practical approach to produce overall cumulative incidence function (CIF) based on estimates from multiple imputed and PS-matched samples.

• 대한전자공학회논문지
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• 제23권6호
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• pp.981-987
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• 1986

This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.