• BMB Reports
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• v.51 no.8
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• pp.412-417
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• 2018

Homotypic cell-in-cell (CIC) structures forming between cancer cells were proposed to promote tumor evolution via entosis, a nonapoptotic cell death process. However, the mechanisms underlying their formation remained poorly understood. We performed a microarray analysis to identify genes associated with homotypic CIC formation. Cancer cells differing in their ability to form homotypic CIC structures were selected for the study. Association analysis identified 73 probe sets for 62 candidate genes potentially involved in CIC formation. Among them, twenty-one genes were downregulated while 41 genes were upregulated. Pathway analysis identified a gene interaction network centered on IL-8, which was upregulated in high CIC cells. Remarkably, CIC formation was significantly inhibited by IL-8 knockdown and enhanced upon recombinant IL-8 treatment, which correlated with altered cell-cell adhesion and expression of adhesive molecules such as P-cadherin and ${\gamma}$-catenin. Together, our work identified IL-8 as a positive regulator of homotypic CIC formation via enhancing intercellular adhesion.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.2-17
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• 1999

Interpolated second order polynomials(ISOP's) are proposed to design efficient cascaded integrator-comb(CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOP's can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOP's are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified half band filter(MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for a programmable downconverter is a cascade of a CIC filter, an ISOP, MHBF's and a programmable finite impulse response(FIR) filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.2C
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• pp.93-98
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• 2011

Currently, The new communication system was very important because of the increasing demand for Internet access. One of these alternatives is the PLC. But, Power Line is not suitable for communication. So, electromagnetic wave is generated from Power Line during flow of communication information. And the electromagnetic wave is interfered with Wireless Communication Service using the same frequency range. To eliminate this interference by used Notch tilter. Wavelet OFDM in another way, while one is used. In this paper, Wavelet OFDM CIC filter used in the CMFB structure by applying a further lowering the value of the side-lobe is proposed to improve performance.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.71-76
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• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1785-1792
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• 2000

In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.1497-1499
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• 2012

전통적인 소프트웨어 개발에서는 초기 요구사항을 정확히 판단하고 분석하는 것이 중요하다. 이를 위해 B.Boehm은 가치혁신 요구공학을 제안하지만, 이는 기존의 개발 방법 기반이다. 본 논문에서는 가치 혁신 요구공학 개선을 위해, 유스케이스 기반의 요구공학 방법을 제시와, 요구사항과 유스케이스의 우선순위 도출 방법을 제안한다. 이를 위해 어려운 시스템 요소(하드웨어와 소프트웨어)를 기본 단위인 유스케이스 요소와, 유스케이스 점수(Use Case Point) 개념을 적용하여 유스케이스 중요도를 도출한다. 그 기본 단위 내의 분석을 통해 쉽게 요구사항 추출 및 우선순위화를 한다. 이는 테스트 단계에서 우선순위화된 테스트 케이스를 적용이 가능한다고 본다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.1239-1242
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• 2012

현재 소비자의 요구에 따라 다양한 타켓 상에서 임베디드 소프트웨어 개발이 폭주되고 있다. 같은 서비스를 제공하는 어플리케이션을 다양한 플랫폼에 맞게 개발하려면 많은 시간과 비용이 소모된다. 또한 이를 위한 테스트 비용도 증가하게 된다. 이는 테스트 비용의 지출이 전체 개발비용에 막대한 영향을 미친다. 그래서 다양한 플랫폼 상에서의 테스트 비용을 감소하기 위해 기존 소프트웨어공학 기법 중 하나인 Model Driven Architecture (MDA)를 적용한 기존 임베디드 개발기법에 테스트 프로세스를 개선 및 강화할 것을 제안한다[1 ][2]. 또한 다양한 타켓에 맞는 이종 테스트케이스 개발에 밑거름이 될 것이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.340-343
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• 2010

스마트폰 어플리케이션은 소프트웨어의 평가를 구매자가 쉽게 확인 및 작성할 수 있어 품질이 매출에 직접적으로 영향을 끼쳐 소프트웨어의 품질을 향상시키기 위해서 테스트가 요구된다. 하지만 기존의 스마트폰 어플리케이션은 테스트 용이성을 고려하지 않고 개발되어 테스트를 위해 많은 비용이 증가한다. 본 논문은 이 문제를 해결하고자 소프트웨어 설계 단계에서 모델변환을 적용하여 테스트 용이성을 향상 시키는 방법을 제안한다. 대상 모델은 UML의 클래스 다이어그램이고 테스트 용이성 측정을 위해서 Binder방법을 사용한다. 적용사례로 안드로이드 기반의 소프트웨어인 SnakePlus를 구현하고, 이를 대상으로 설계 모델을 모델변환을 하여 테스트 용이성을 향상 시킨다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.72-74
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• 2010

임베디드 시스템은 하드웨어 리소스가 매우 작다. CPU속도가 느리고 메모리 크기도 작다. 이런 환경에서의 소프트웨어는 최적화된 크기를 가지고 수행속도가 빠르며 병목 현상이 없어야한다. 이렇게 코드를 최적화하기 위해서는 현재 코드의 문제를 찾아내야 한다. 이것은 정적 분석으로 만으로는 부족하고 프로그램을 수행시켜가면서 정보를 수집하는 프로파일러가 필요하다. 기존의 프로파일러는 윈도우, 리눅스 상에서 수행되는 응용프로그램을 위한 것이기 때문에 저급 임베디드 시스템에서 프로파일러를 수행할 수 없다. 본 논문에서는 이러한 문제를 해결하기 위해서 임베디드용 프로파일러를 설계 및 구현 한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.