• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2252-2258
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• 2016

CCMP(centralized conferencing manipulation protocol) enables adding and removing conference participants, changing their roles, adding and removing media streams in conference system. In this paper, by using extended CCMP, a new distributed conference system architecture which can be used to multiple servers distributed conference system in SIP(session initiation protocol) environment has been presented. In this study, according to increasing number of participants, a new extended CCMP architecture which can distribute conference system loads to multiple servers dynamically to decrease loads of servers has been designed. This extended CCMP architecture also can add dynamically new servers from the prepared servers pool. Furthermore, new conference information data format which can represent extended CCMP has been designed, and exchange procedures of extended CCMP control messages which can distribute loads between servers have also been presented. The performance of the proposed system has been analysed by simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8A
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• pp.640-647
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• 2009

IEEE 802.11i is an amendment to the original IEEE 802.11/b,a,g standard specifying security mechanism by stipulating RSNA for tighter security. The RSNA uses TKIP(Temporal Key Integrity Protocol) and CCMP(Counter with CBC-MAC Protocol) instead of old-fashioned WEP(Wired Equivalent Privacy) for data encryption. This paper describes a design of a communication security engine for IEEE 802.11i MAC layer. The design includes WEP and TKIP modules based on the RC4 encryption algorithm, and CCMP module based on the AES encryption algorism. The WEP module suffices for compatibility with the IEEE 802.11 b,a,g MAC layer. The CCMP module has about 816.7Mbps throughput at 134MHz, hence it satisfies maximum 600Mbps data rate described in the IEEE 802.11n specifications. We propose a pipelined AES-CCMP cipher core architecture, which has lower hardware cost than existing AES cores, because CBC mode and CTR mode operate at the same time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.547-553
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• 2019

Presence server should process massive SIP subscription request messages and massive presence event notifications from presence resources in real time. Therefore multiple servers architecture is needed for presence service system. In this paper, an architecture of multiple servers presence service system using SIP based CCMP control messages for lowering presence server load level has been presented. In this system, each presence server exchanges current load status using CCMP control messages, and total system load according to variance of users number and amount of presence resources has been effectively distributed processed. The CCMP control messages has been optimally designed to control presence servers, and exchange procedures of these control messages between presence servers has been also presented and the performance of the proposed multiple servers presence service system has been analysed by experiments. The result shows that average presence subscription processing time reduced from 40.8% to 69.2% and average presence notification processing time reduced from 29.4% to 62.7%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.367-370
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.11i wireless LAN security. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining)mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 25% compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 15,450 gates, and the estimated throughput is about 128 Mbps at 50-MHz clock frequency). The functionality of the CCMP core is verified by Excalibur SoC implementation.

• ALGAE
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• v.33 no.2
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• pp.181-189
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• 2018

Emiliania huxleyi (a haptophyte) is the most abundant coccolithophore species that produces delicate calcite scales called coccoliths. In this study, we identified several candidate genes associated with coccolith production by comparing the transcriptomes of the calcifying (CCMP 371) and non-calcifying (CCMP 2090) strains of E. huxleyi. Among the candidates, genes highly expressed in CCMP 371 were identified. To confirm whether these genes are associated with calcification, we modulated coccolith production in CCMP 371 by culturing it at different calcium concentrations. At an ambient (10 mM) concentration of calcium in the growth medium, CCMP 371 sustained its calcifying ability. However, at a low (0.1 mM) concentration or absence of calcium, there was no calcite formation, demonstrating that calcium-limiting conditions negatively affect calcification. We also evaluated the expression patterns of the putative genes in cells grown at different calcium concentrations by quantitative reverse transcription polymerase chain reaction. In addition, we showed that the growth rate of cells cultured under calcium-limiting conditions does not differ from that under ambient conditions. Further studies are required to investigate the roles of the putative calcification-associated genes at the molecular level.

• Archives of Pharmacal Research
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• v.29 no.1
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• pp.73-79
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• 2006

This investigation was undertaken to study the effects of oral administration (3 weeks) of Collybia confluens mycelial powder (CCMP) produced by a submerged culture on plasma glucose and other biochemical parameters in streptozotocin (STZ)-induced diabetic rats. Antidiabetic and hypolipidemic effects were proportionally increased with the increasing concentration of the CCMP for oral administration. The CCMP, at the dose of 400 mg/kg BW, substantially reduced the plasma glucose level by as much as 33.1 % as compared to the STZ-induced diabetic rats group. It also lowered the plasma total cholesterol, triglyceride, and low density lipoprotein (LDL) cholesterol by 22.9%, 19.9%, and 37.3%, respectively. The levels of total cholesterol and triglyceride in liver were reduced to the extent of by 13.5% and 18.8%, and the activity of alanine transaminase (ALT) and aspartate transaminase (AST) was decreased by 48.8% and 37.2%, respectively, under the influence of CCMP. The general components of CCMP were found to contain 26.18% carbohydrate, 3.67% crude ash, 4.02% crude fat, 22.55% crude protein, and 43.58% dietary fiber. The amino acid composition of the CCMP was also analyzed in detail.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.390-393
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• 2006

IEEE 802.11e 과 IEEE 802.11n에서 data의 높은 전송률을 구현하기 위해 Block Ack와 frame agegation 과 같은 새로운 mechanism이 논의 되고 있다. 이러한 mechanism은 각각의 MPDU processing 마다 짧은 응답시간을 요구한다. 본 논문에서는 위의 새로운 MAC을 지원하는 IEEE 802.11i를 위한 효율적인 CCMP 설계를 제안한다. 제안된 설계에서는 한 AES-CCM core에서 MIC calculation 과 정보 암호화가 128bit씩 순차적으로 수행되어지는 mode toggling 접근을 채택했다. 본 설계에서는 응답시간이 44 clock cycle의 짧은 짧은 시간으로 줄었다. 또한 하나의 AES-CCM core를 사용하고 낮은 주파수에서 수용할만한 data throughput과 응답시간을 얻었기 때문에 하드웨어적인 복잡성과 전력 소모를 줄일수 있었다.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.